Has anyone here used the 5LP for controlling a Constant current sink circuit using internal op amp and dac.
I am considering the circuit below
DaHu,
/odissey1's Gate_Drive_Tune circuits is creative but may be a bit difficult to tune at run-time when the ambient temperature changes or self-heat thermal effects of the FET occur.
Additionally, the control feedback loop on the Gain_Offset PGA requires constant SW intervention. Depending on your application for a constant current load, the additional latency may cause some control loop glitches.
Below is a CCL circuit I've used on the PSoC for projects to place a load for battery testing. It is tuned for 0mA to 100mA. It is very similar to your FET-based proposal. Since the feedback signal is connected to '-' input of the opamp, the control loop latency is dependant on the RC of the Rccl_fb_1 and the input capacitance of the PIN_ccl_fb_1 and the propagation delay of the OpAmp_ccl_1.
Carefully changing Rcs_1, Rccl_1 and Rccl_ctl_1 resistor values as well as a power transistor for Qccr_1 it should be possible to change the operational range from 0mA to 4A for your application.
Here's a current plot of the above circuit where I have commanded the CCL to 18mA for a duration of 1.04 secs.
Here's another perspective of the FET versus Transistor debate: In linear mode,
- Power dissipation is virtually identical for a FET or Transistor.
- Transistors have wider linear gain control between cutoff and saturation. That's why they are still used in Class A and Class AB amplifiers in audio.
- FET could have a slight edge over transistors with lower effective Rds @ saturation. This could mean lower Pd when driving the CCL at maximum load.
Len
