unble to pack the design into 2 UDBs

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unble to pack the design into 2 UDBs

user_3568726
Level 2
Level 2
First like given
‎Jul 12, 2018 12:06 AM
‎Jul 12, 2018 12:06 AM
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I created a new project, when I compiled, there is some errors, shows that unble to pack the design into 2 UDBs,but My schmetic is very simple. resource meter shows that UDB  still has free space, just like picture below, how to solve this problem? thanks very much.PSCO.jpg

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Re: unble to pack the design into 2 UDBs

Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked
‎Jul 12, 2018 02:34 AM
‎Jul 12, 2018 02:34 AM
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An UDB consists of several different parts, LUTs registers, datapath, macrocells, ALU etc. Some of the resources seem to have been spent while others are still avail. >Click on the "+" sign in front of the UDB in the resource list to get more information.

A brief estimation: I agree with the fitter, tihis design might need more than 2 UDBs. Try a larger chip as the CY8C4245.

Bob

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