Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
Hi, one of the PSoC4 limitations is that it's not possible to use a clock signal for any other purpose than clocking a component. I need a gated clock output for my component. I know that the usual way would be to use a clock two times faster than needed, but I wonder if it's possible by another way. I tried to implement a "any-edge T-FF" in Verilog, which is "accepted" when compiling the design, but it throws a notice about a combinational loop. I haven't tested yet if this really works, I first want to figure out which is the better way. If I have to use a two times faster clock, how is it implemented in the component? Currently I've a state machine which reacts on every clock pulse, but if the above applies, my component must only react on every 2nd clock pulse. Regards, Ralf