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PSoC 4 MCU

Contributor II
        Hi, one of the PSoC4 limitations is that it's not possible to use a clock signal for any other purpose than clocking a component. I need a gated clock output for my component. I know that the usual way would be to use a clock two times faster than needed, but I wonder if it's possible by another way. I tried to implement a "any-edge T-FF" in Verilog, which is "accepted" when compiling the design, but it throws a notice about a combinational loop. I haven't tested yet if this really works, I first want to figure out which is the better way. If I have to use a two times faster clock, how is it implemented in the component? Currently I've a state machine which reacts on every clock pulse, but if the above applies, my component must only react on every 2nd clock pulse. Regards, Ralf   
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Honored Contributor II

PSoC Sensei has a nice blog post about handling clocks as data in PSoC4: http://www.cypress.com/?rID=80799

   

Maybe it helps you out (even though he doesn't directly explain gating a clock, you can easily add this to the examples).

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Contributor II
        Hi hli, thank you. After reading the blog and several forum threads I think it's the best way to use an input clock which is twice the output frequency. Regards, Ralf   
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