I understand the main steps to enable the Capsense Tuner as found in the "Using the Tuner GUI" section of the CapSense_CSD data sheet.
However, I'm ha...
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I understand the main steps to enable the Capsense Tuner as found in the "Using the Tuner GUI" section of the CapSense_CSD data sheet.
However, I'm having difficulty getting the EZI2C component to fit in the CY8CKIT-042. If I attempt to connect the added EZI2C component signals scl and sda to the KitProg I2C by using Port P3[0] and P3[1], the project won't compile without errors. It will compile if I use P4[0] and P4[1] then jumper those signals on the kit. What other options are available to add tuner functionality to a CY8CKIT-042 without external jumpers?
Following are the modifications I made to the CE202479 code example, along with the modified code attached.
Main steps:
1) Enable Tune Helper
2) Add EZI2C component
3) Add code to Main.c
{
CyGlobalIntEnable; /* Enable global interrupts. */
CapSense_CSD_TunerStart();
/* All widgets are enabled by default except proximity widgets.
* Proximity widgets must be manually enabled by calling
* CapSense_1_EnableWidget() API, as their long scan time is
* incompatible with the fast response required of other widget
* types.
*/
while(1)
{
CapSense_CSD_TunerComm();
}
}
4) Build and Program
5) Start CapSense Tuner
Note: The EZI2C component will connect by default to P4[0] for scl and P4[1] for sda
The I2C on the KitProg (PSoC 5 on the kit) is connected to port P3[0] for scl and P3[1] for sda.
Attempting to route the EZI2C to Port 3 (P3[0] and P3[1]) causes fit problems.
As an alternative, the two ports can be connected externally using jumper wiresl
6) Add jumper wire for scl between P3[0] and P4[0] via J3-4 to J3-10
7) Add jumper wire for sda between P3[1] and P4[1] via J3-5 to J3-9
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Mar 18, 2022
Solved
