PSoC™ 4 Forum Discussions
I am experiencing low signal strength when using the CYBLE-224110-EVAL in short range (i.e. PA/LNA disabled). My setup has it connected to the Pioneer CY8CKIT-042-BLE.
I have a simple BLE component that's advertising at 0dB TX power. RSSI (as checked on multiple known-good Android handsets) when right next to it is around -77dB - it should be more like -40.
If I enable the PA/LNA, then the RSSI improves massively to better than -30dB. However, the current will exceed our budget.
Is there any reason the signal strength is so poor with the PA/LNA disabled?
Show LessHi,
Please help to review the attached schematic
The interfacing between keypad and microcontroller (LPC1788 from NXP) is provided through I2C communication.
Please advise if any changes to be made. Thank you
Regards
Maruthi
Show LessI need the HTS and ECCN number for a Cypress kit "CYALKIT-E02".
But, I can't find "CYALKIT-E02" in the below HP.
http://www.cypress.com/knowledge-base-article/how-do-i-get-hts-and-eccn-number-cypress-kit-kba81250
Thank you.
Show LessSo, where is the errata sheet for PSoC4000? I've searched the site high and low, and found nothing. Despite that, I already found some actual bugs:
- Documentation for the SROM syscall to setup clocks is wrong (TRM "Document No. 001-89309 Rev. *C" page 144). Docs say that this syscall takes a pointer to memory, and there I write param. This never works. Passing the actual param directly (like for "checksum" system call) in SYSARG register does work.
- Either documentation for SPCIF_GEOMETRY is wrong, or the chip has a bug where it reports the wrong value. My CY8C4013SXI-400 (which has 8K of flash) reports this register's value as 0x0001003f. As per register doc sheet (Document No. 001-90002 Rev. *C) that means it has (0x3f + 1) * 256 = 16384 bytes of flash. Of course in reality the chip has 8 (and as a test, I do indeed get a fault if I read past 8K)
- If I use the "Load Flash Bytes" SROM syscall shortly after boot, and point it to an area of flash where i put in the proper params to load 64 bytes of data into the write latches (0x0000d7b6, 0x0000003f) but I DO NOT WRITE THE NEXT 16 WORDS (let's assume i am ok writing whatever garbage was there into flash) , SROM locks up (actual cortex-m0 core lockup bit set and all). However, if those same words of RAM have ever been written before since boot (by core or by the MEMAP) no lockup occurs. (Yes, flash clock is properly set up. Yes, literally writing zeroes or any other values to these bytes immediately before or long before the syscall makes it work properly/)
Given all this, I am guessing at least a few more issues exist. is there a list?
Show LessI am currently trying to develop software for a PSoC 4 to communicate with a MCP2515 CAN controller; however, I cannot get the SCB SPI block to work. I have a PSoC 4200 Prototyping kit that is programmed via the USB boot loader.
I have copied the blocks, the pin mapping and the code from this example and placed it in the project I created that was bootloadable. I made some small modifications where I replaced the LCD to a uart print out so that I could attempt to do some rudimentary debugging.
The project should simply put a list of SPI commands into the slave tx buffer, then into the master tx buffer, and then should read and print from the opposing rx buffers. This does not work, all I get is 255 for every byte that comes through when they are clearly not meant to be of this value.
Further down the track it will be necessary to have this function interrupt driven so I can set masks on the CAN controller and then get messages transmited etc, but I have no implemented this at this stage.
I have attached the example project for your reference.
Regards,
Show LessHi all,
Is there a way to increase the 3~16 bit SPI master data width limit to 20 bits maybe more? I worked around this issue by using the shift register component with the SPI master to get what I needed done but running into some timing issues.
I know that I can make custom components but would like to avoid doing this. Any ideas?
Thanks,
Eric
Show LessHi,
I'm searching for an easy way to extract/put uint16 form/in CAN Messages/Mailboxes
Before (with other Platform) I do this:
UB12=(*(short *) &CAN_Receive_Data[1]);
UB24=(*(short *) &CAN_Receive_Data[3]);
(*(short *) &CAN_Send_Data[1])=UB12;
(*(short *) &CAN_Send_Data[3])=UB24;
Regards,
Michael
Show LessI have started looking at the BLE (OTA) over the air firmware update system provided by Cypress and am trying to find information on embedding the host down loader into our mobile application. Does anyone know of any examples to do this? All I can find is the example using the CySmart mobile application.
Thanks
-Chris
Show LessI'm new to BLE so forgive me. Do all custom services need to be listed in the advertisement packet? I have an application wit a custom service and the Device Information Service. If I remove the Device Information Service from the advertisement packet, CySmart on my Android still seems to know that it's there. How?
I am developing an embedded peripheral as well as a matching smartphone app. If both the 4200BLE and the smartphone know the UUIDs, is it necessary to advertise them in the advertisement packet?
Thanks!
Show LessHello support team,
my hardware setup is the "CYBLE-212019-EVAL EZ-BLE PRoC Evaluation Board" with the "CY8CKIT-042-BLE" Kit.
I have a workspace with two projects. One for the bootloader and one for my application. For programming i use UART communication.
Programming of my application over UART works fine with the "Bootloader Host" tool shipped with PSoC Creator and with the example tool "UART Bootloader Host GUI" which is delivered with the UART Booltloader example (AN68272).
My problem is that i have to reset the device manually and my final device should never have a reset button or any other button, only CapSense.
If i debug the bootloader and set a breakpoint in the function "Bootloader_HostLink" of the file "Bootloader.c" at "Bootloader_COMMAND_EXIT" in the switch statement, it never reaches this lines of code after successful bootloading.
But there is the needed "CySoftwareReset()" and this should reset the device after bootloading.
I have tested both above mentioned tools.
If i take a look at the source files in the folder "cybootloaderutils" in the main directory of PSoC Creator at file "cybtldr_api2.c" in function "CyBtldr_RunAction", there is a call to "CyBtldr_EndBootloadOperation()" after the bootloading operation which generate and send the "EXIT COMMAND"...
I have implemented a own tool with the mentioned source files but this does also not reset my bootloaded device 😞
Why is the "EXIT COMMAND" not received by the bootloader?