PSoC™ 4 Forum Discussions

I have a very simple design (attached).  I'm comparing implementing a shift register (as a delay line) vs a series of DFFs.  The delay line runs off of a routed clock (asynchronous to HFCLK).

The issue I'm having is with shift register component (v2.30).  Using the shift register from a routed clock gives the warning:

Warning: sta.M0021: Design01_timing.html: Warning-1350: Asynchronous path(s) exist from "CyRouted2" to "CyHFCLK". See the timing report for details. (File=<...>\Design01.cydsn\Design01_timing.html)

In addition, the shift register does not work as expected:

    
• When using the routed clock (as is in the attached project):     
        
  • The 2-bit shift register delays the data pulse by ONE clock period (NOT EXPECTED)
        
  • The 2 DFFs delay the data pulse by TWO clock periods, as expected
       
    
• If I change the routed clock to a New Clock created from HFCLK (NOT as is in the attached project):     
        
  • The 2-bit shift register delays the data pulse by TWO clock periods, as expected
        
  • The 2 DFFs delay the data pulse by TWO clock periods, as expected
       
   

My misunderstanding is in how the ShiftRegister component works.  Specifically, why is it using the HFCLK at all?

Brian

hi,

i have been  making Temperature sensing product on psoc-4. Here i use in built SAR ADC for sensing.

There is a two type of sensing.

1) RTD

2) Thermocouple

i got accurate reading of RTD and thermocouple with different parameter of ADC like;

RTD:

1) SAMPLE MODE:          HARDWARE TRIGGER 

2) AVERAGING MODE : ACCUMULATE

THERMOCOUPLE:

1) SAMPLE MODE:          FREE RUNNING 

2) AVERAGING MODE : FIXED RESOLUTION

i cant changed this setting from code.

can i do this with code on run time whenever i needed??

Hi,

I am new to this forum, and thought i would give it a go.

I have a problem with the Sar multiplexer on PSoC 4. The problem is that it doesnt log the actual values that i can meassure with a voltmeter. In addition, i am sampling on all 8 channels, and the offset from RealValues to SampledValues is different on each channel.

I think it might be problem with the setup of the SarMux.

Can anyone offer some insight? Something i havent thought about?

Note: The project is based on an SD-card example, and i have added an lcd-screen as well. Comments in code are in danish.

Purpose: The purpose of my prototype is to meassure the increase of resistance in a wire, after each bend. The PowerRelay bends the wire from side to side, and i sample each X'th cycle. I made a voltage divider to where i am meassuring the voltage after the wire i am testing, and before a 1K_ohm resistor. With Ohms law i should be able to determine the resistance of the wire by meassuring the voltage between the "two" resistors.

SampleValues:

Cycle: 0 Data: 4424, 4468, 4, 4468, 2240, 4071, 1405, 4468,
Cycle: 4 Data: 4457, 4466, 1161, 4466, 3126, 4426, 2515, 4463,
Cycle: 8 Data: 4457, 4466, 1191, 4466, 3176, 4428, 2544, 4463,
Cycle: 12 Data: 4455, 4466, 1193, 4466, 3130, 4426, 2504, 4463,
Cycle: 16 Data: 4457, 4466, 1025, 4466, 3246, 4428, 2511, 4461,
Cycle: 20 Data: 4457, 4466, 1178, 4466, 3109, 4424, 2526, 4463,
Cycle: 24 Data: 4457, 4466, 1047, 4466, 3248, 4428, 2493, 4461,

(samples in cycle 0 is the aim, and for this óne instance, was meassured correctly)

Hi,

I try to implement the following scenario:

boots -> process a task in ACTIVE mode for exectly 2 sec -> deep sleep for 5 sec -> task for 2 sec -> deep sleep 5 sec and so on.

This works great with WDT (wakeup from deep sleep after counting WDT intervals until 5 sec are reached) and a one shot timer (to time the 2 sec task duration).
But if I add BLE functionality into the design, something does not fit any more. I invested already two days into it, and read of course all the available PDFs (BLE getting started + Low-Power Modes and Power Reduction Techniques) , I analised the LPM example project but it uses the WDT differently then me.

I prepared a use case project (with oth) to analyse the problem, which uses LEDs and UART for logging.

So without BLE, where everything is fine, the following expected LED sequence can be observed:

    

GREEN (task) for 2 sec
BLUE (deep sleep) for 5 sec 
during BLUE phase above 4 WHITE flashes every 1 sec (WDT interval ticks, reentering deep sleep)
end of BLUE phase above 1 WHITE double flash (wake up from deep sleep)

and so on...

   

UART logs the following sequence, (the single point after each WDT tick stays for reentering deep sleep mode).

    

Do something...
Try to sleep...

    

WDT tick: 1
.
WDT tick: 2
.
WDT tick: 3
.
WDT tick: 4
.
WDT wakeup

   

 Now if I enable BLE (un-comment #define ENABLE_BLE in main.h), I observe the following pattern

    

GREEN for 2 sec
GREEN for 2 sec
BLUE flickering for about 3 sec
during BLUE phase above 2 WHITE flashes every 1 sec (WDT interval ticks, reentering deep sleep)
end of BLUE phase above 1 WHITE double flash (wake up from deep sleep)

    

and so on...

   

UART logs the following sequence

    

Do something...
Try to sleep...
Update GATT database...
Do something...
Try to sleep...

    

WDT tick: 2
....................................................
WDT tick: 3
..............................................................................
WDT tick: 4
.............................................................................
WDT wakeup

   

One can see many single points between WDT ticks, so the program tries reentering deep sleep very often but stays there only for a short time. I suppose it is because of the BLE subsystems interrupts, which would be fine if the average power savings were OK which I did not measure now. Am I correct with this assumption? How can I tune the intervals here, I did not catch this in the docs.
But what really bothers me is the fact, that work phase (GREEN) occurs twice without any sleep phase between, and that the deep sleep phase itself is shorter as expected (something above 2 sec instead of 5).
Eventually the program crashes after some time sooner or later. I am not experienced enough yet to debug this 🙂

Why does BLE interfere with the WDT timer so radically? I would expect, that the WDT does it work in background without any distortions using LFCLK. Giving WDT higher interrupt priority than BLESS or changing the LFCLK source from WCO to ILO does not make any difference in the pattern.

Is there anything I can do to fix my design? I will appreciate any optimizations.
What can I do to better understand the BLE low power behavior?

My project is attached to this post.

Thx

Edit: I found a logical error, now the timings are OK but the connection from a GAP client (CySmart app) can not be established reliably, especially during sleep phase. I would say this is my actual problem now + the random crashes after long running times.