PSoC 4 MCU

Hi all,

We are facing one issue of hanging touch panel.

When capsense is not working, other ISR is working.

How can I detect a fault in cap sense ?

How to get an error code in this situation?

How to solve this issue ?

Hello Team,

Kindly let us know if CY8CKIT-042-BLE kit supports simultaneous multi keypress functionality.  If yes you can share an example code with us.

We have a requirement wherein we have to press two keys (e.g. Menu up + Power on/off) simultaneously for 10 seconds to pair kit with the BT Device.  

We have seen BLE HID keyboard example but it sends only one key at a time.

Hello everyone,

I am developing at a very low level communication between the PSOC-4 and a SD card via SPI protocol. In this whole process I'm at the point where I need to transfer 514 bytes per SPI to the SD card (MOSI).

The concept is very simple but I have a lot of problems with increasing the data rate of the SPI block. The whole setup works fine below 1.5 Mbps, but when increasing to 4Mbps with oversampling at 16 (3Mbps real) the DMA transfer stops working properly. I have tried to narrow down the problem as much as possible and it seems that the problem is in the behaviour of the DMA block.

To rule out that there is no problem with the SPI block I have increased to 8Mbps data rate and used the CPU to communicate with the card and everything has been successful. I would like to remind you that at lower speeds of 1 and 1.5 Mbps everything works fine with the DMA. At first I have worked with these low frequencies to be able to analyse the communication with a logic analyser. My idea was, that once everything works fine, to simply increase to the maximum speed.

In order not to go into too much detail I can reduce the problem to a simple SPI transfer with DMA (forgetting that the communication is with an SD). I simply need to transmit 514 bytes of data over the MOSI line at over 3 Mbps.

The information flow is simple, once everything is ready, the DMA descriptor is validated and the channel is enabled to start the transfer to the FIFO register of the SPI module. The problem is that in the interrupt function that is indicated to the DMA it jumps with an error. The error produced is obtained with TxDMA_GetDescriptorStatus(0);. The normal behaviour is that the DMA generates an interrupt with that flag to CYDMA_DONE. Instead it generates two interrupts with the flag to CYDMA_INVALID_DESCR.

The weirdest thing is that it works at low data rates and doesn't work at high data rates. I think I'm missing something and I don't understand what.

The part of the code that involves this problem is first of all the initialisation:

struct DataPacket{
//    char token;
    char data[512];
    char CRC[2];
}__attribute__((packed));

struct DataPacket multipleWriteBuffer;


int main()
{
TxDMA_Start((void *)&multipleWriteBuffer, (void *)SPI_TX_FIFO_WR_PTR);
TxDMA_SetInterruptCallback(TxDMA_Done_interrupt);
CyIntEnable(CYDMA_INTR_NUMBER);
CyGlobalIntEnable;
.....................

The function to be triggered by the DMA interrupt is:

void TxDMA_Done_interrupt()
{
    descriptorStatus=TxDMA_GetDescriptorStatus(0);
    descriptorStatus=descriptorStatus & 0x00070000U;
    switch(descriptorStatus){
        case CYDMA_DONE:
        {
              DMAFlags=1;
        }; break;
....................................
        case CYDMA_INVALID_DESCR:
        {
            DebugPin_Write(0);
            InvalidDescriptor++;
            DebugPin_Write(1);
        }; break;
    }
}

when I need the to start data transfer:

        TxDMA_ValidateDescriptor(0);
        TxDMA_ChEnable();

The DMA descriptor configuration is:

The SPI advanced tap configuration is :

And less relevant to the case is the spi basic tab:

Conection between SPI and DMA module:

I think including an image of the logic analyzer may help to notice when the InvalidDescriptor event occurs. Remember that I have a debug pin that throws a pulse when this event occurs so I can detect it in the logic analyzer.

General view of the transmission, without zoom:

A zoom in on the area where these events occur:

In summary: every time I start a transfer, the interrupt with the CYDMA_INVALID_DESCR error is raised.

Do you have any idea what is going on?
Thank you for your help.

Has anyone had any luck implementing Zlib compression on a PSoC board? I'm looking to use this method to transfer a large amount of data sent via BLE. 

Are there any Cypress libraries out there to easily perform this sort of operation? 

Hello Everyone, 

Cypress has listed this APCN with no real descriptor as to the action/cause for change. I am using a 4100S chip that is on this list and need to understand what the effect will be on  this micro. The lead time went from 28 weeks to 104, with no reason for it. Has anyone any idea as to what is occurring? 

Hello, further to a question I asked (https://community.cypress.com/t5/PSoC-4-MCU/Reversing-proxmity-sensing/m-p/270896#M39101).  After weeks of testing, I found that the CapSense values are very sensitive to the voltage of the power supply.  At 3.8v the raw value could be 8000, while 3.7v could be 1000 and even lower when approaching 3.6v. 

Since my system runs off a 3.8v battery as the power supply (connected to VDD of CY8C4245 directly). Is there any way to get a stable value from CapSense even the supply voltage drop a little? Like an internal regulator or something?  

Thank you!

I tried to connect CY8CKIT-42-BLE-A with CYALKIT-E04 by reffering the CYALKIT-E04 S6AE102A and S6AE103A Evaluation Kit Guide, A.3: Programming Using PSoC programmer.

But the firmware programming of BLE dongle was failed due to this error: "The hex file does not match with the aquired device". The hex file I used is BLE_Dongle_256K.hex. 

I don't know the cause of the error. Should I use other hex file?

Also, I would like to send door sensor data over BLE to dongle by using the door sensor included in the sensor board of CYALKIT-E04 kit.

Do I need other firmware program for that?

If anyone has some examples, I would appreciate if you share the example.

I am very grateful for your advice. Thanks in advance.

Shu

Hi,

Regarding the GND electrode and the shield electrode, the mesh width and the distance between the meshes are described in the reference manual in a fixed manner.
What is the rationale for this value?

Also, what are the negative effects of using a solid pattern instead of a mesh for the shield electrode?

Regards,

Naoaki Morimoto

Hello,

Looking at J9 at SCHEM1 seems to represent J9 on SCHEM2 which seems to suggest that depending on the jumper of J9, the PSoC 4 and PSoC 5LP chips will be powered by either the USB's 5VDC or the 3.3VDC via the LDO power supply system. The jumper chosen on J9 will represent the VDD volatge throughout the parts connections. (Please confirm if I am assuming this correctly!)

In SCHEM3, we have VCCD??? Where does this come from???

Thank you 

All help appreciated

r