PSoC™ 4 Forum Discussions

Hi, Community 

I would like to use the device configurator in Modus tool box 3.0 to make the SAR ADC look like the attached figure.
What settings do I need to make?
There are two settings I would like to achieve.
The first is single-ended unsigned integer, 12 bit resolution.
The second is unsigned integer with differential input, 12 bit resolution.
I would like to know how to set up Vneg and the wiring design.

The figure is from this manual : https://www.infineon.com/dgdl/Infineon-PSoC_4_Scanning_SAR_ADC_(Scan_ADC)_1.0-Software%20Module%20Datasheets-v03_01-EN.pdf?fileId=8ac78c8c7d0d8da4017d0eb260ff2b12

The device I am trying is a PSoC4100Smax. I am using the architecture guide as a reference : https://www.infineon.com/dgdl/Infineon-PSoC_4100S_Max_PSoC4_Architecture_Technical_Reference_Manual_TRM-AdditionalTechnicalInformation-v01_00-EN.pdf?fileId=8ac78c8c83cd30810183ef1400e220a9

Best Regards,

Chihiro Tatebayashi 

Dear Guys,

I add a deep sleep mode in my program, and I can wake up the program after deep sleep.

but when I try to wake up the program with interrupt of GPIO's falling edge, here comes up with a error:

Pin Error: (Mixed Interrupt Signal. Cannot assign 'UI_BTDETECT(0)' with Interrupt Signal UI_BTDETECT to physical port 0 where 'Com_PonRX(0)' with Interrupt Signal Com_PonRX is already placed.).

the GPIO's pin shows power on/off, when there is no power connected to device, the pin(Com_PonRX) keeps High level, and when the device powered on, the pin will be pulled to Low level.

can anybody tell me what's wrong with the setting? how should I deal with GPIO interrupt?

Dear guys,

In order to save power, I need to set the MCU into deep sleep mode when there is no working for MCU.

I found a API (CySysPmDeepSleep())of entering to deep sleep mode from code example, and I just use it simply in my code.

but it seems I got same current consumption with previous software which doesn't contain deep sleep API.

Now the current consumption will always be 5/6mA from VDD(3.3V), but my target is less than 10uA.

so I got failure in this trying.

can any body tell me how to use this API to enact deep sleep mode?

here is my function about how to set mcu to deep sleep mode:

void SleepCmd(void)
{
if((CHMode == M_CHOFF)&&(UI_BTDETECT_Read() == 1)&&(F_ONOFF == 0)&&(BATCloseLEDCount == 0)&&(OCPLEDCount == 0))
{
SleepDelay++;
if(SleepDelay >= 200)
{
SleepDelay = 0;
Meas_ENOP_VREF_Write(0);

CySysPmDeepSleep();
}
}
else
{
SleepDelay = 0;
Meas_ENOP_VREF_Write(1);
}
}

Hi, 

I would like to know when PSoC4100S Max will be added to the Power Estimator ?

I look forward to the addition of new devices to this useful tool.

PSoC 4 Power estimator tool  

Best Regards,

Chihiro Tatebayashi

@Vasanth @AnjanaM_61 @AnushaTR 

I have two PSoC4 chips (CY8C4244LQI-443 and CY8C4245LQI-483) these can be independently programmed using the MiniProg4. If I connect both of them at the same time to a 10pin connector and try to select one of the chip in the Programmer and try to flash it the programming process fails. In this scenario, only one of the chip with higher memory is automatically detected by the Programmer (ie, the manual selection gets overwritten). Can anyone suggest a solution for this?

I'm working on a design that needs a 25 bit shift register with PLD output taps at 0, 8, 12, 16 and 24.

First stage is a D-FF.  But it appears that a 24 bit UDB SR can't provide taps, nor can 3 8 bit UDB SRs provide the 12 bit tap.  So my architecture is D-FF, SR 8, 8 D-FFs, SR 8.  Now the questions:

1.  When I designed it, the build tool gave me a warning about async clock crossings.  All of the above is connected to a single clock, yet the SR 8 outputs are, it claims, clocked from CyHFC.  I'm a bit lost on how that got there.

2. Using the above topology, the tools are going to use duplicate macro blocks for the two SR 8s, which would have been combined if I had used an SR 24.  Further, there is no need for load, store or reset, so it really shouldn't need any macro cells.

3. I'd probably be better off just configuring two UDBs, but I haven't figured out how to do that (how to get symbols to place on the schematic.

4.  I'd probably prefer to do the whole thing in Verilog and forget the schematic, but I haven't been able to find a Verilog primitive for the UDB.  Presumably there is one for the ALU and separate ones for the counter and other parts, possibly even for the Control, Status and FIFOs, which aren't needed in this part of the design.

5. The UDB document claimed there would be a tab at the bottom of the schematic to access the Verilog code generated by the page.  I had hoped I could use that as a model for any or all of the above shortcomings, but no such tab appeared.

I'm fairly proficient at hardware design and Verilog (not to mention embedded firmware development, but this is my third experience with PSoC Creator and my first experience with UDBs, so I'm in a learning curve.  I did build one sample project to get me oriented.

I have attached a screen shot of the intended design.  It is part of a larger hardware design for a 4200L

is there any way to do the same with psoc 4 that looks like this image?

Hello,

i have a problem in getting up FreeRTOS for PSoC4:

the vTaskDelay(pdMS_TO_TICKS(500)); -> never return

MainTask runs only onces.

Main_Task_2 is working as aspected.

all Libs are up to date.

Have anybody a sample Project for PSoC4 and FreeRTOS I am wondering that is no Example availible?!

BR

Andreas

Hi guys!

I'm trying to implement a bootloader where I can reprogram the internal psoc flash with a program stored in an external flash.

I'm following this document on the steps that I need to program, I don't need all of them since its not an external programmer, I am programming from "inside" the chip. I get the hex file from the HexFile Parser program so I guess the hex file is correct.

I can write on the flash rows but once I finish programming it, nothing happens. What can I be missing?