PSoC™ 4 Forum Discussions

I understand what a combinational loop is, but I don't understand where I'm getting it.  This is in a UDB Datapath.  The issue is that various instructions use Option A and Option B comparisons. and the results of those comparisons is used to select the next instruction.  I don't see a combinational loop there, because the path from instruction address to option selection should be registered, so the behavior should be clearly defined.  Here are the specifics

Option A is A1 compares to A0

Option B is A1 compares to D1

Instructions 2 and 3 use option B, all others use option A

There are three outputs:

Min = A0 < D0 (not part of the option selection)

Threshold uses the less than of the options

Equal uses the equal of the options

ADDR1 = ~Min & (Threshold | Equal)

It gives me two warnings about combinational loops and breaking them

Breaking the loop at \Decode:Manchester:HeaderCnt_select_1\/main_3 --> \Decode:Manchester:HeaderCnt_select_1\/q

Breaking the loop at \Decode:Manchester:HeaderCnt:u0\/cs_addr_1 --> \Decode:Manchester:HeaderCnt:u0\/ce1_comb

I can't find the exact references either in UDB documentation, or in the Verilog version of the UDB, so I'm lost where to go next.

The only thing I know right now is that if I change all 8 instructions to use only Config A, the warning goes away.  But I really do need to switch to Config B.  I have three comparisons that I need to do at various times with this UDB:

1. Comparing A0 < D0 for a minimum value, particularly at the end of the sequence.  This doesn't involve the config option.

2. Comparing A0 <= A1 where A1 is used to store the peak value of A0

3. Comparing A1 to D1 to make sure that the peak value met the minimum expectation.

So my approach was to forgo the A0 <= A1 comparision while A0 < D0, because any valid peak should rise above that.  That way after capturing the peak and coming back down to where the possibility of a higher peak no longer exists, it switches to option B so I can determine if the peak was high enough.  It is a minor nuisance during the rising time, but that is manageable.  But because the A0 <= A1 comparison directs the next step to see if A1 needs to be saved, both the less than and equal outputs need to be part of the address.  But again, I fail to see the combinational loop, since the address to instruction mapping should be clocked.

What am I missing, and how do I get around it?

Wilton

Hi，All

    I have a question: When using P0.7(RX) and P3.6(TX) of CY8C4025AZI-S413 as analog serial ports, 10pcs IC has been tested with the same firmware, but some communication is normal, some communication is abnormal? What are some of the reasons why this might happen? Thanks！~

https://infineon.github.io/psoc4pdl/pdl_api_reference_manual/html/group__group__tcpwm.html

Looking at the above page, there is a description that it is possible to measure using Timer/Counter as shown below,
However, the input of Timer/Counter is only the internal clock of the microcontroller, and the frequency of the externally input PWM cannot be selected,
I am having trouble understanding how to actually achieve this.

　Use this mode whenever a specific timing interval or measurement is needed.
- Measuring frequency of an input signal
- Measuring pulse width of an input signal

Please let me know if there are any samples or documents that are applicable.

I would be grateful if you could point us to any documentation or usage related to the "Built-in" feature.

Hi,

I have enabled UART interruptes and I am tracking RX FIFO not empty. When I enabled interrupts then CyDelay() stopped working. The program would stop when calling CyDelay() function.

Is this a known issue and what is the solution?

Thank you

Hi,

I was prototyping a project on a breadboard using CY8CKIT-042-BLE dev kit with CY8CKIT-143A module board plugged in.
The project prototype was powered from a 12V (stepped down to 5V) mains earth referenced ATX power supply and the 042-BLE dev kit was powered from those 5V via VIN pin.
At some point I plugged the dev kit to a PC via USB as well to programm it, so it was powered from those two sources at the same time.
I left it like this and went on to modify the prototype on the bradboard and managed to short it.
A 1.5A fuse blew up at the 12V power input stage of the prototype.

After this event I separated the dev kit from the project but it powered up Mass Storage\CMSISDAP mode (breathing green LED). I managed to leave this mode by holding the reset switch switch.
- Now after powering up this green LED is slowly blinking (ca. 1 Hz) which means "bootloader mode".
- Programming this target device from PSoC Crator is not possible anymore, because the device can not be connected.
- PSoC Programmer software detects bootloader mode: "Connected at 23:08:34 | KitProg bootloader device is detected".
- PSoC Programmer -> Utilities -> Upgrade firmware seems to succeed and the LED is permanently ON. Here are the status messages of the upgrade process:

Successfully Connected to KitProg/0E1B194A02012400 at 23:36:53 | KitProg Version 2.21
Opening Port at 23:36:51 |
Connected at 23:36:50 | KitProg/0E1B194A02012400
Disconnected at 23:36:48 | Bootloader device
Firmware Update Finished at 23:36:48 |
| Succeeded
| Verifying...
| Upgrading...
| Initializing...
Firmware Upgrade Started at 23:36:19 |
Firmware Upgrade Requested at 23:36:19 |

- But programing from PSoC Creator is stil not possible with the following error

"There was an error running port acquire: PSoC device is not acquired! Check connection of the chip to the programmer"

- Other CY8CKIT-143 and CY8CKIT-143A modules I have lying around make no problems at all, so I imagine the 042-BLE dev kit as such has not been demaged by the short circuit

The question 🙂 Did I fry this particular CY8CKIT-143A module plugged in during the short circuit and can thor it away, or is there a way to execute some sort of "factory reset" on it?

I would like to know any special methods or tips for creating host interfaces to communicate over various ports to a PSoC. I know that all interfaces (SPI, I2C, UART...) support standard interface drivers. Can someone help me confirm that, and also tell me if there are any examples available?

Hello

I'm using a CY8C4246AZI-M445.  When configuring one of the opamps, I am receiving about 160mV off noise on the output when inputting 0V.  The configuration is non-inverting with a gain of 20.  I'm using external resistors and the output of the opamp connects to a pin.  I'm using an oscilloscope to view the input and output.  How can I solve this?  

thanks

Shawn