PSoC™ 4 Forum Discussions
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Hi
I currently have development boards for CY8C4248(4200L) and CY8C4246(4200DS).
Who has a sample code for transferring ISO7816 to USB on CY8C4248 or CY8C4246?
Or do you have any ISO 7816 sample code on CY8C4248 or CY8C4246?
Alternatively, where can I find it?
Thanks
Lucas
Show LessI just installed PSOC Creator 4.4, created a workspace and a project and a library.
But when I go to my top design schematic in the project the component catalog does not have a tab for my library, only the Cypress library and OffChip library. I have made sure my library is check in the dependencies. I've restarted PSOC Creator several times. Closed and reopened the schematic. But I cannot get it to find my library.
A related detail, I created the UDB (which is now in the library) as a component in the project. It wanted to make it TopDesign.cyudb, even though I had a top design schematic already. I can't envision a cyudb ever being the top of the project. I did give it a better name (the process isn't very obvious). And it did show up in the appropriate tab in the component catalog, but the program refused to drop it onto the schematic. So I decided it needed to be in a library.
So a related question is whether it did need to be in a library, since is was a rather specialized component for that project, and if not, how to make it in a manner that the top schematic will allow it to be added as a symbol.
This whole thing is getting frustrating, because I don't know which magic button to push to get this UDB in my design. It is the inevitable consequence of trying to make things too user friendly by hiding details the user isn't supposed to need to know--except they inevitably do.
Thanks,
Wilton
Show LessHi Community, I'm currently facing an issue with UART data transmission and Clocking of DelayMs function. When I don't remove the delay function, UART transmission works well but the data is not saved in EEPROM and when I remove delayMs function, UART doesn't works but The data is saved into EEPROM. I'll be sharing the code if required.
Show LessDear Sirs and Madams,
I understand that PSoC Creator provided an API to acquire the sensor capacitance.
Similarly, could you tell us how to get the capacity of the sensor used in ModusToolbox, or could you provide us a sample code?
Regards,
Show LessHi, Community
Is there any tool that can easily adjust audio data such as stereo or mono when checking the operation of a wave file created in c on a PSoC4100Smax (or any other device with I2S functionality)?
I would like to use Borland compiler etc. to create the original data, but it should be a tool bundled with the Modus tool box.
Even if not, I would like to know if there are any tools you would recommend for creating the wave file.
Of course, I would prefer that they be in a free environment.
Best Regards,
Chihiro Tatebayashi
Show LessHi, I have to find PSoC 4 for IoT application. So I interesting in 4100 Family but I need to know some points,
1. If which part number have same package, same numbers of I/O but difference CPU clock speed and difference Flash/RAM size for example CY8C4146LQI vs CY8C4125LQI. Are these two part interchangeable?
2. What point that I need to care when I need to design to use pin compatible part in PSoC 4 family?
for addition, I'm not sure What difference between 4100 vs 4100s family?
Thank you very much. s
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Hi~
My question is like as title
Does touch IC ship to customer as virgin status(No bootloader, No basefirmware) ? or Does touch IC ship as including bootloader?
My customer use CYAT81658-64A-S48.
Many thanks
BRs
Show LessI have identified a possible bug in the way UDB editor instantiates state machines with reset. I noticed that while reset was held high, the state machine would toggle back and forth between states 0 and 1 at the clock rate. Later I used the supplied verilog code as a basis for a different state machine I was building and noticed similar behavior. Upon looking at the code I found the following:
always @ (posedge clock)
begin
if((Reset) == 1'b1) begin // Reset Condition
HeaderState <= State_0_Clear;
end
case(HeaderState)
That means that Reset will force it into state 0, but then fall through into the case statement, which can then change the state. Technically is bad (possibly illegal) Verilog, because it is could be making two registered assignments in the same clock cycle. The normal way that this would be implemented would be:
always @ (posedge clock)
begin
if((Reset) == 1'b1) begin // Reset Condition
HeaderState <= State_0_Clear;
end
else begin
case(HeaderState)
This makes the reset exclusive to the case statement and will hold the state machine in reset and otherwise inactive until it is released.
Show LessI can not even find the product on Infineon webpage.
There is no documentation whatsoever, just one yotube vid of one guy selling a modified version and all in the programming GUI it says "it is unknown how this setting influences the controller". Is there any REAL Infineon page with their products ALL AND COMPLETELY listed there with small PDFs that tell you how it works out or is this just an Infineon thing to not care about this?
It was the second most expensive BLDC on the market and there isn't even a manual anywhere.
Please help me out if you know what I am doing wrong(, move the question to a more fitting topic which i couldn't find) and have a nice day!
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