Hi.

   I want to handle some registers in CY8C4045AZI-S413.

     But there is no detailed information of them in TRM /Family Datasheet/Module datasheet,etc.

     For example, in a control register, every bit should be introduced.    

Is there such a document?

客户用CY8C4146LQE-S423去做项目，目前项目处于调试阶段，客户想确认下Cypress 是否有用于量产的烧录器，和debug用的是否有区别？

Hello Everyone,

I Built the one project , It have capsense, I2c , UART, timer blocks but i found the one warning like setup timing violation of cyHFclk.

please tell me how to avoid this warning. (should i worried about it?)

Timing details attached with this case.

thanks ,

Manish

Please answer below.
The same question is written in English and Japanese.

※PSoC 4100S and PSoC 4100S Plus: PSoC 4 Architecture TRM, Document No. 002-10621 Rev. *G 21

・English
It is described as "VDDD and VDDA should be shorted externally.
"In the PSoC4100SP, can you not set “VDDA (5.0 V) ≠ VDDD (3.3 V)”?

・Japanese(日本語)
"VDDD and VDDA should be shorted externally."と記載されています。
PSoC4100SPでは、"VDDA(5.0V) ≠ VDDD(3.3V)"といった設定はできないのでしょうか？

Regards,

I am porting my firmware from EFM32 MCU to PSOC 4. I am not familiar with PSOC 4 and it looks like Cypress PDL does not support PSOC 4. I want to know if Cypress provide a C library for PSOC 4 like EFM32 emlib library?

Thanks.

Please answer below.
The same question is written in English and Japanese.

・English
Is this correct?
"SID185 vRISEIPOR" is the reset release voltage.
"SID186 vFALLIPOR" is the voltage to reset.

・Japanese(日本語)
以下、正しいでしょうか？
「SID185 vRISEIPOR」は、リセット解除の電圧。
「SID186 vFALLIPOR」は、リセット状態にする電圧。

Regards,

Hello,

my simple DCC decoder project gives a

"Warning-1367: Hold time violation found in a path from clock ( Clock_1(FFB) ) to clock ( \Bit_Timer:cy_m0s8_tcpwm_1\/tr_compare_match )."

which I don't understand.

My project:

The top DFF samples 80usec after a rising edge the DCC line

and the DFF below generates the according clock.

Its clk is fed by the negative cc signal, to be shure,

that DCC_Data is stable.

After 100usec, DCC_Clk is brought to LOW.

Static Timing Analysis in attachment.

I designed a loop powered transmitter with XTR116, I made this application with Cy8C4025azi-S413. I used PWM block to generate DC for XTR116, but the PSOC does not work properly on supply provided by XTR116, Almost 24mA current PSOC draws which XTR unable to supply. The system clock I reduced to 6MHz. PWM clock is 12mhz.

I expect the PSOC must work on low power at 5mA in active mode