PSoC™ 4 Forum Discussions

Hello,

I want to know the status of each SWD port in the setting that enables SWD port in PSoC4.

The attached image was considered based on the following information.

- I/O State on Power Up

  PSoC® Analog Coprocessor Architecture Technical Reference Manual (TRM) [Document No. 002-10404 Rev. *C January 9, 2019]

https://www.cypress.com/file/273431/download

  P.72 [7.6 I/O State on Power Up]

- Acquire the Chip After Hard Reset

  Programming Specifications [Document No. 002-22326 Rev. *B]

  https://www.cypress.com/file/409521/download

  P.43 [4.3 Step 1A – Acquire the Chip After Hard Reset]

- Internal Register

Re: About processing of debug pins (SWDCK, SWDIO)

I want to know about the following things.

Q1. Pin status with nothing(Host etc.) connected to SWD port.

       If Input Buffer is enabled on the SWD port, pull-up / down of the input is necessary to prevent IO destruction.

       However, although it confirmed on the evaluation board, it was in High-Z state.

       As my guess, isn't the Input buffer in an invalid state?

       (Because of that, it looks as High-Z state)

Q2. If the device is reset in the Reset cycle Mode / Power cycle mode, does SWD Port enable the input buffer and internal pull-up/down?

Q3. If the Host does not issue a Line Reset signal to the SWD port, does the SWD port disable the input buffer and internal pull-up/down?

       And does the state of IO become High-Z state?

Best Regards,

Kenji Takahashi

Hello.

Q1)

Is there PSoC4S sample project using guard sensor?

Please provide it if there is it.

Q2)

Could you please let us know FW development procedure when guard sensor is implemented?

CSD component(above V3.x) has not widgets for guard sensor.

Should user add normal button sensor as guard sensor if they use guard sensor?

And should user add code to main.c about PSoC behavior after guard sensor touch status becomes “1”, according to their design specification?

And there is no API and component configure setting for guard sensor, right?

Best Regards.

Yutaka Matsubara

Hello,

We would like to reset if the program is jumped to the unused flash area.

Do you have any good ideas about that?

Best regards,

Yocchi

Hi,

I'm using PSOC4 SAR ADC sequencer block and I don't understand how the two averaging modes (accumulate vs fixed resolution) work.

What I'm trying to do is to oversample a channel 16x and increase the effective number of bits by 2 (from 12-bit to 14-bit). I understand there are assumptions about the white noise distribution but let's assume all those things for this discussion. What I have discovered is that if I use the fixed resolution averaging mode, the result after oversampling 16x is still a 12-bit number. What I would like is to get a 14-bit number to work with after all the accumulate and decimate actions in the ADC block.

I know I can write an ISR to do the accumulate and bit shifting in software but that will oversample all channels.

Is there an elegant solution to what I'm trying to achieve here using the built-in ADC block? I noticed that the averaging mode has an accumulate option. What should I expect from this option? Is the end result already averaged or simply accumulated? What software processing is required to convert the result under accumulate option to the 14-bit number I want?

Thanks in advance,

John

Hello,

I tried whether Program counter is jumped to Hard Fault or NMI if PSoC4S runs in the unused flash area like

"Execution of an Undefinded instruction" of Cortex™-M0+ Devices Generic User Guide(ARM DUI 0662B).

The unused flash area is filled 0x00 by Compiler(Linker?) of PSoC Creator.

I launched the debugger and breaked after running. Then I changed PC(Program Counter)  to the unused flash area.

After that, I ran it again. Consequently, PC is running in the while(1) of  CY_ISR(IntDefaultHandler) in Cm0plusStart.c.

The errno macro seems to mean 0 value. but, there is no 0 value in "errno.h".

Does it mean that "Execution of an Undefinded instruction" is done?

Best regards,

Yocchi

Hello

what BLE event is representing code 0x10012 ?

I am using a PSOC 6 with the PDL middleware library, in the file cy_ble_stack.h the general events listed with prefix 0x100 are shown from 0x1000 to 0x1004, then those with prefix 0x200 and so on. I have seen this code event popping up in uart terminal while debugging, just between a connection and the discovery while running in central role from PSOC6.

Thanks.

Fausto

I'm working on a project where we have 6 CapSense buttons. Our pads consist of an outer ring and a center pad with a metal dome on the outside ring. During CapSense Mode, I would like the outer ring/dome to act as a CapSense button which I have working fine. However, I would like to dynamically change the mode of the CapSense pins to be inputs so the buttons could then become mechanical buttons (The dome gets pressed down and shorts the outer ring with the inner pad).

Is this something that would be possible? If so, how could I go about implementing this? I know you can change input/output pin configurations/modes on the fly, but I can't find anything on changing from CapSense to input/output pins.