PSoC™ 4 Forum Discussions
I'm using PSOC4 - CY8C4245PVI with external clk of 10Mhz at P0.6. This is working fine.
But my UART (SCB) is not working. I've configure UART for 115200baudrate.
Show LessHello
I receive the below error when I try to "Generate Application". I'm using auto routing and I'm not locking any pins. In my design, I have one op-amp, two 4x1 analog hw muxes and an ADC. I cannot seem to generate this design without errors. The error appears to be some kind of digital routing issue. The only digital signals I have are a control register that switches the 2 muxes and two clock inputs to the muxes. There is also a UART block.
--------------- Build Started: 08/24/2019 23:29:48 Project: Uart_multiplexor3, Configuration: ARM GCC 5.4-2016-q2-update Debug ---------------
cydsfit.exe -.appdatapath "C:\Users\shawng.WAGNER\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "C:\Users\shawng.WAGNER\Documents\PSoC Creator\Workspace02\Uart_multiplexor3.cydsn\Uart_multiplexor3.cyprj" -d CY8C4245AXI-483 -s "C:\Users\shawng.WAGNER\Documents\PSoC Creator\Workspace02\Uart_multiplexor3.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o0 -v3 -.fftcfgtype=LE
Elaborating Design...
HDL Generation...
Synthesis...
Tech Mapping...
ADD: pft.M0040: information: The following 15 pin(s) will be assigned a location by the fitter: \UART:rx(0)\, \UART:tx(0)\, pin1(0), Pin2(0), Pin3(0), Pin4(0), Pin5(0), Pin6(0), Pin7(0), Pin8(0), Pin_1(0), Pin_2(0), Pin_3(0), Pin_5(0), Pin_6(0)
Analog Placement...
Analog Routing...
Analog Code Generation...
Digital Placement...
Digital Routing...
Error: rtr.M0004: E1216: Routing of net __ZERO__ Failed. Source : :udb@[UDB=(0,1)]:pld1:mc2.q, Sink : :m0s8scbcell_0.miso_m
Error: rtr.M0004: Error routing design: Routing Failed (12)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
--------------- Build Failed: 08/24/2019 23:29:53 ---------------
Show LessHi
Below is the captured waveform of MBR3116 CS0 pin, which is connected to a sensor.
It shows a frequency-changing waveform. Is that coz MBR3 uses PRS clock?
Could the clock frequency be decreased by modifying some setting parameters of MBR3?
Thanks.
BR
Grace
Show LessHello,
I would like to change period and compare value directly in TC interrupt handler with API during running Timer/Counter of PSoC4000S.
Is there no problem?
Or can we only use swap of PWM instead of Timer/Counter?
Best regards,
Yocchi
Show LessHello,
I am using PSoC 4200M series (CY8C4247AZI-M485). I was trying to use the ADC. Just to get a feel for it, I uploaded the ADC_SAR_Seq_Die_Temp_PSoC4 example code in the PSoC creator 4.2 to check the measured voltage. When I ground the ADC pin the ADC does not read 0mV, instead it reads any value ranging from a few tens of mV to about 3-4V. However when I give it a voltage equal to the reference voltage (VDDA) it reads it properly. Can someone please guide me on what might be happening and how to fix it?
Show LessHi All,
I am using a PSoC 4100S device with CapSense.
There seems to be two CapSense components CapSense[v6.0] and CapSense_ADC[v6.0].
What is the difference between these two components?
Regards
Show LessCan I connect a mux input to GND internally or do I have to create a pin and connect to GND?
We have a project that nicely builds on two PC’s (in less than a minute)
On another PC the exact same project takes 1 ½ hour to do the same. On this one two nets seems to be splitted – according to the log – no clue why and cannot find any information about it either.
It is the Code generation step after 35% that takes lots of time (although it is not taking much system resources).
Good Cases:
- No net splitting
- Have both PSoC 4.1 Update 1 and PSoC 4.2 installed
Bad Cases:
- Net Splitting
- Fresh PSoC 4.2 installation
Attached is the log info and the environment info for both PC’s. Compare snips below.
One additional problem is that two pins must be left auto assign for the code generation to run, see below.
Net_3941 is the SPI:MOSI net
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Is it possible to erase SFLASH memory in each proggraming with Psoc programmer? I am using psoc4.0 .