PSoC™ 4 Forum Discussions
I found in my design, PSoC4200 is very easy to be burned. Sometimes if short power to GND carelessly, there would see spark and smoke from PSoC chip. I'm think it is burned due to the over current? I didn't add fuse on power line.
Show LessHello all,
I've been following AN68272 on how to use my microcontroller (STM32) to update the EZ-Serial Firmware running on the Cypress CYBLE-222014-01 Module to V1.1.1. So far, I've converted the stack and application .cyacd files of the 1.1.1 EZ-Serial Firmware into a string array respectively and included the file in the program. I've also included the cybtldr files that were given with the UART example in AN68272.
These are the steps I take on my MCU host:
1) Check the firmware version using EZ-Serial API call "ezs_cmd_system_query_firmware_version()"
2) If the firmware version is not the version I get from modules that are 1.1.1 (0x101011a) then I switch the device to DFU mode over UART using ezs_cmd_dfu_reboot(2)
The next steps is where it gets confusing.
I think I need to update both the stack and the application of the EZ-Serial PSoC module (is this required to go to V1.1.1 - or just the Application?). When I update the module in OTA mode using the Cypress Smart Mobile Application, the device resets after updating the stack and continues with an application upgrade. This makes sense according to the documentation.
My thinking to implement this over the MCU is:
3) Bootload the string image of the Stack after device is in DFU mode
4) Wait for EZ-Serial Device to reset (maybe some sort of delay)
5) Bootload the string image of the Application
If someone has attempted something similar, your insight would be really appreciated.
Thanks!
Rishi
Show LessHello and let me start by saying I think this is a signal integrity issue, but cannot explain it.
I am communicating with a BMA253 accelerometer and on read the data in the receive buffer flips the LSB to a 1 if it is a zero. On the scope I see the correct commands and data in both directions, but there is ~0.5V of rolling noise on the signals, not sure where that is coming from. I have tried every combination of control the SPI component has. The device accepts modes 0,0 and 1,1, tried late sampling, more and less over sampling, median filter, different clock rates (will come back to this). I even tried adding a third byte to the read, to ensure that the CS was sufficient during the transfer. There is an SPI FLash memory on the buss, but I have not even tried talking to that yet, I assumed this would be simpler. I have attached my bundle.
Other topics on this, I cannot get the SPI to function below 1.5Mbs, the BMA253 device has no min frequency, and the SPI UCB DS does not specify min and max frequencies, yet below 1.5Mbs there is no SPI activity, can you help me understand the difference.
ECO vs IMO, which is a better clock, my next test will be to run the system from the IMO not the ECO and see if the noise on the clock get any better, which is the cleanest internal clock?
Thanks for looking, this is really an issue, and like I said to start, most likely a signal integrity problem, but it only flips the LSB, which is odd, if it were truly noise on the data line, other bits would be flipping.
Herb
Show LessHello,
Our customers want to use TunerAPI data transmission and custom data transmission to change the CapSense settings and monitor status.
The host MCU normally rewrites the CapSense dsRAM via user-created I2C buffer.
When debugging, start Tuner from the PC and rewrite the CapSense dsRAM.
As you can see, dsRAM can be accessed in two ways. Are there any cautions to this configuration?
Please advise on proper procedure.
We have already communicated the following points to customers.
a) When switching between Tuner and User Custom I/F, read the entire dsRAM and check for any unintended parameter changes from the previous values.
b) CapSense_GetParam (uint32 paramId, uint32 * value) and CapSense_SetParam (uint32 paramId, uint32 value) should be used for parameter read/write.
c) Do not call CapSense_Stop () and execute CapSense_Start () again in order to activate the changed parameters from the user's custom I/F.
Best Regards,
Naoaki Morimoto
Show LessHi all,
[1] Ext Vref(P1.7)
How much is the ampacity of Vref(P1.7) of CY8C4247LTI-L475?
[2]Internal Vref(1.024V)
Is it possible to to output the internal Vref(1.024V) outside CY8C4247LTI-L475?
If possible, how much is the current of internal vref?
Thanks,
Show LessI’m looking for explanation or confirmation of a couple issues found while using CE222306 - PSoC 4 I2C Master
1) There appears to be an interrupt preventing the For loop in Main.c from proceeding beyond the I2C Write
- Moving the “Cycle through the LED Colors” section before the “Send packet with command to the slave” section allows the colors to cycle.
- Running the debugger, the code never goes past the command: if (TRANSFER_CMPLT == WriteCommandPacket(command)). Executing that command likely causes an interrupt that resets back to the beginning of Main.
- It appears the interrupt routines are drafted: mI2C_SCB_IRQ and mI2C_I2C_INT.c and cyapicallbacks.h. It would be helpful to have an ISR pre-set to let code proceed through the main loop. My work-around was to put the I2C Write command as the last command in the Main For loop.
Note: I’m guessing the I2C Read command may generate a similar interrupt. The project doesn’t allow code to progress past the I2C Write to get to that I2C Read, so it hasn’t been tested. Colors on the target I2C Slave kit change without the read.
2) The While Loops in the I2C Write and Read routines have no escape clause. The code can hang waiting for Master Complete.
- Recommend adding a timer or counter here.
I appreciate the examples Cypress has developed and the community as a repository for issues and concerns found that can help to improve those code examples.
Greg
Show LessHi all,
I have a question about SARADC input range of CY8C4247LTI-L475.
I will use the single end mode of SARADC.
The setting of SARADC is as follows.
---------------------------------------------------------------------
Vref select: Internal 1.024 volts, bypassed
Single ended negative input: Vref
Single ended mode range: 0.0 to 2*Vref(2.048V)
---------------------------------------------------------------------
I'd like to know the analog signal input range.
Does PSoC4 break when analog signal exceeding 2.048V is input?
(VDDA is 5V or 3.3V.)
Best regards.
Yasu
Show LessI have a doubt with bridge control panel code for EZI2C slave. I made a code it is collecting data but not the correct data from the cypress. example the raw count it shows is not same as the raw count in the tuner graph. I have attached the code , readings and graph.
Show LessHi,
I have 4 CYBLE-2241100 BLE modules and i am advertising them with different TX level and device names.But when i am checking for the advertising device in the cysmart and nrf app. I am able to see the advertising devices but the BD_ADDR is same for all the devices (00:a0:00:88:99:77).
Why is the BLE device address same?
If it is same how to limit the devices in central with respect to their address ?
How can i search devices based on the advertising device name?
Thanks,
Uma
Show Less