PSoC™ 4 Forum Discussions
Hi ,
I am using CY8C4128LQI-BL543 trying to measure the ECO frequency with a frequency counter. I am using the reference guide for it. unfortunately, there is not reference to how to route the ECO to the GPIO for measurement, although it is mentioned in the reference document that it is needed as part of the Xtal trimming
the reference document is here:
https://www.cypress.com/file/139476/download
and the reference for routing is here:
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Hello, I require a Bilateral switch as per a 4066, I have tried using the creation wizard, but limited editing of the functions prevents me from creating this component, is it possible, or is there an example in existence already?
Kind Regards
Show LessHi ,
For an application without having the ability to pair with the device (since we are using one Master phone to scan multiple peripheral sensors), we would like to use application level encryption. I know that encryption and decryption using SW is very long , therefore usually using HW block for that. Is there any way which I can use the encryption/Decryption HW block directly ?
Couldn't find any reference for it online.
Show LessHello, I need experts assistance for Pcap button layout.
Because of the limited board area, we plan to use 4-layer board for a 8 buttons, 5 LEDs and 2 connectors (have other PWM signal, LED signals......). see attached mechanical drawing.
Follow AN64846 <Getting Started with CapSense>, the top layer is CapSense; layer2 is CapSense traces; layer3 is hatching Ground; bottom layer is other components and traces.
Our mechanical design has 2 connectors exactly underneath 3 buttons. According to <Getting Started with CapSense>, it says:
.........
* Isolate switching signals, such as PWM, I2C communication lines, and LEDs, from the sensor and the sensor PCB traces. Do this by placing them at least 4 mm apart and fill a hatched ground between CapSense traces and nonCapSense traces to avoid crosstalk.
* Avoid connectors between the sensor and the controller pins because connectors increase CP and decrease noise immunity.
.......
With a hatching Ground plane layer3, Can the connector directly under the button? And should all other traces (on bottom layer) at least 4mm apart from CapSense (on top layer) and CapSense traces (on layer2)?
Thanks.
Chang Cao
Show LessDear all:
We use 4024 as a multi-Capacitive touch key processor. It generate an interrupt signal when touch down event be detected.Now we need check response time of our mass product.Can you tell me how to test ?
There is a planstic cover on the touch key sensor which was connect to PCB by FPC.
Thanks!
Li Min
Show LessHi,
I have opened the Temperature sensing project for CY8CKIT-147, but I have received the error on ADC_SCAN (Old version block), What can I do ?
See the attached file.
Show LessHi everyone,
I am currently facing a problem on making fft works using CMSIS DSP library. Basically, I want to convert real time data from my sensor into frequency data by using FFT CMSIS DSP library. However, it only works for the first loop. I debug the code and somehow the program is still running after the first loop but i cannot find the location of the code where the program is running after first loop (Step Over). Does the FFT messed up the memory location of every function in the program or i cannot call the FFT function more than one time? Thank you.
Show LessWe have a device, based on CYBLE-222005-00. The firmware was created long time ago, following AN97060, so that it allows OTA upgrade of the BLE Stack and the Application. Since then, the PSoC Creator Components have been updated several times. Firmware development was started in PSoC Creator 4.1 and later continued on – PSoC Creator 4.2.
I was recently doing a code review and checking the firmware generation flow. When I repeated the instructions from AN97060 for an OTA Upgradable Application with added Upgradable Stack OTA Bootloader, I discovered one difference in the “cm0gcc.ld” file.
In our project file we have:
CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(675, CY_FLASH_ROW_SIZE);
while in the example, the same line is different:
CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(685, CY_FLASH_ROW_SIZE);
The following questions arise:
1. Why is that? I do not remember changing that file. Does this value depend on the version of any of the PSoC Creator Components? For example, I see that the BLE Component in the example is of version 3.30, while in our project this component is of version 3.60.
2. Should I expect any problems as a result of using 675 instead of 685?
3. Is there any different way to determine and use a correct value for CY_CHECKSUM_EXCLUDE_SIZE than copying the “cm0gcc.ld” file from the example?
Show LessHi,
I am currently in the process of implementing a communication component in verilog. The component has 3 digital inout terminals. To this i want to attach 3 different bidirectional pins.
Throughout the communication process, i will need to change the drive mode of the pins connected to the terminals. How can this be achieved in verilog. Any hints are greatly appreciated.
regards,
Martin
Show LessWhat is the difference between the boards
CY8CKIT-044
https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/CY8CKIT-044/428-3391-ND/5237072
2015-CY8CKIT-044-ND
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