PSoC™ 4 Forum Discussions
Hi,
I saw that the PSoC 6 is part of PyOCD, any chance to get Cypress/Infineon's help to also add the psoc 4 series?
Even though MiniProg is one of the nicest probes out there, It's nice to be able to run Daplink v2 GitHub - ARMmbed/DAPLink on your own MCU to flash psoc 4, 5lp & 6'es in various scenarios where a miniprog or segger wont fit the bill.
Thanks
Show LessI've got some questions about the IIR Filter on CapSense block.
1- It appears that I have to make some coefficient adjustments for widget calibration. However, I do not have detailed information about what these coefficient values should take for proper filtering of high frequency spikes to prevent false triggers and noise for my application.
2- I've made some research about the CapSense block on Cypress from the datasheets, but I couldn't get detailed information about the usage of this filter. It is clearly briefed that this filter is used for eliminating the high frequency noise. but I couldn't see about the information about what these filter coefficients should be in any situation.
There's just an information about the raw count coefficient that the lower count value results in lower noise. According to my understanding, this coefficient parameter is set
as low when the environment of touch widget has lower noise. According to these info, Should I set this raw count coefficient parameter as high in higher noise ? I'll be appreciated if you illuminate me on this matter.
3- On the CapSense block, I do not understand exactly in which cases the parameter entered in the regular baseline coefficent section is used. However, according to the information in the above datasheet visual, as far as I understand, the parameter entered in the coefficient part of the IIR Filter section of the coefficient in the relevant field is the same. If it is like I understand, I would like to find out why there are two different parameter parts in the above CapSense block visual. I do not fully understand the part after the comma of the sentence highlighted in yellow in the baseline filter settings section. I'll be appreciated if you illuminate me also on this matter.
Show LessRegarding, the CY8CKIT-142 PSoC 4 BLE Module Schematic.pdf, looking at the psoc 4 ble module schematic as attached, the values of load cap C23 and C24 at 32.768KHz are 36pF and 18pF, so I'm wondering why used it differently, although I generally know by using the same load cap value.
Thank you!
Tony Kim
Show LessHi,
In the capsense tuner, it possible to modify the Tx clock frequency, number of sub-conversions, idac gain, ... under the sensor parameters left menu, and send the new values to device.
1. Is there a way to to this through firmware, or to get and read the current values of those parameters? I tried using the capsense_getParam API with the macros defined in the capsense_registermap.h header (it works for other advanced param like finger threshold) but none give access to those parameters I believe.
In the CSX tuning example for PSOC 4, It mentions that I have to check the value of the IDAC code after setting up the TX clock frequency. https://www.cypress.com/file/504331/download p.6
2. I see every element in my widget has a different IDAC value. what is the difference between the IDAC value and the IDAC gain (and mA/bit??), I cannot quite grasp what they mean?
Thanks a lot
Show LessWe have completed the design of our CSD liquid level sensing solution based on PSoC4, it works great, and we can easily detect levels, temperature has minimal effect and we are satisfied with our design.
Now production has asked us to provide a solution to test the unit. Our sensors are connected via wires, and the main board with the CPU is what is to be tested.
We need advice on how we can test to see if the capsense is functional? Test engineering wants to put 50mil diameter pads connected to the traces, please confirm that this will not be a good idea as this will add stray capacitance? Also, we are not sure what signal they could inject to determine if the captouch was working. Also, I am skeptical that a precision capacitance can be shown to ask the unit to detect.
Below is a view of the connectors for the off board widgets, the pad shown on J1 is being requested on either side of the PCB.
Do you have any ideas or suggestions on how to production test this solution. We do have one idea, to model the capacitance of the PCB with no connections and then again with a connector removed and another with the resistor removed and a third with a different resistive value.
Show Less
Please provide recommendations to avoid premature battery failure using BLE Modules.
The issue is premature battery failure along with resetting using CYBLE-012011-00.
BLE soft component (2.10) has been updated since the project was written and programmed into fielded units.
I wasn't able to find errata showing a fix for power savings associated specifically with an update to the latest version of the BLE component, (3.30). Where else might there be a power leak? Has anyone experienced similar issues?
Thanks for your help!
The application sends out a broadcast message (beacon) every 5 minutes and then sleeps.
The current profile and the average current draw is roughly 2.9uA
I have found AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications @ https://www.cypress.com/documentation/application-notes/an92584-designing-low-power-and-estimating-battery-life-ble . Any additional suggestions or confirmation that updating the BLE component from 2.10 to 3.30 will improve battery life, are appreciated.
Show LessHi,
こんにちは、
One of my customer is investigating CY8C4024PVS-S412 for their project.
As the datasheet states that this device has 5 TCPWM, the customer is expecting to generate 5 PWM output.
But they seem to have had hard time to implement this set-up and asked us for help.
私のお客様に CY8C4024PVS-S412 を検討されている方がおいでです。
データシートによると 5つの TCPWM が搭載されているということで、
お客様は 5つの独立した PWM 出力を生成することを期待されています。
しかし、試されたところ上手くいかなかったようでお問合せをいただきました。
So I tried with PSoC Creator v4.3.
例によって PSoC Creator v4.3 で試してみました。
The first schematic
Looks ok to me
先ずは回路図、
問題なさそうです。
But, I could not assign LED_5, which is for TCPWM[4] the 5th TCPWM.
しかし、5個目の PWM (TCPWM[4]) につないだ LED_5 のピンが設定できません。
Even auto pin assign returned error fit.M0059: FFB and IO placement failed: Failed to find a valid placement for LED_5(0).
自動アサインで走らせたところ、M0059 という上記のエラーが返されました。
Then I checked the data sheet,
No wonder, both tcpwm.line[4]:0 and tcpwm.line_compl[4]:0 are assigned to non-existing pins, namely P2[0] and P2[1].
ここでデータシートを確認したところ
なるほど、tcpwm.line[4]:0 も tcpwm.line_compl[4]:0 もデバイス上に存在しない P2[0] と P2[1] にアサインされています。
So I tried to bypass P2[0] to P2[7] by using SmartIO
それならば、SmartIO を使用して P2[0] をデバイスに存在する P2[7] にバイパスしてみました。
Schematic / 回路図
Pins / ピンアサイン
Note: This time I could assign LED_5 to P2[7] as I planned,
but SmartIO pin seems to be floating
今回は無事 LED_5 を P2[7] にアサインすることができました、
しかし SmartIO の内部ピンの接続先が浮いているようです。
And when I tied to compile, I got following errors.
そして、アプリケーションの生成を行ったところ下記のエラーが返されました。
Now my question is
Would someone teach me if there is a way to use all 5 TCPWM output in this device, CY8C4024PVS-S412?
さて、今回の私の質問なのですが、
CY8C402PVS-S412 で 5つの TCPWM の出力を全て外部に出す方法はあるのでしょうか?
Best Regards,
24-Sep-2020
Motoo Tanaka
Show LessHello,
I have a problem setting up an emulated eeprom in a PSOC-4 BLE project, that implements OTA (launcher + stack + application projects).
In the application project I have created the emulated eeprom as specified in the doc:
- Added an Emulated EEPROM component on TopDesign.cysch with the following parameters:
* EEPROM size = 128 (actual eeprom size is 256 bytes)
* Redundant copy = No
* Wear level factor = None
- Configured the "Bootable" component:
* Checksum exclude section size (byte) = 256
- Created, as global variable in main.c:
const uint8 Em_EEPROM_em_EepromStorage[Em_EEPROM_1_PHYSICAL_SIZE]
CY_SECTION(".cy_checksum_exclude")
__ALIGNED(CY_FLASH_SIZEOF_ROW) = {0u};
The problem is that the following assertion in the linker script (cm0gcc.ld) fails:
ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.")
This is what the output of the linker command is:
(...)
arm-none-eabi-gcc.exe -Wl,--start-group -o C:\Users\EricBohnes\git_repositories\power_reader_mcu\PowerReader\PowerReader_application.cydsn\CortexM0\ARM_GCC_541\Debug\PowerReader_application.elf .\CortexM0\ARM_GCC_541\Debug\main.o .\CortexM0\ARM_GCC_541\Debug\ota_mandatory.o .\CortexM0\ARM_GCC_541\Debug\load_control.o .\CortexM0\ARM_GCC_541\Debug\app-ble.o .\CortexM0\ARM_GCC_541\Debug\app-adc.o .\CortexM0\ARM_GCC_541\Debug\app-console.o .\CortexM0\ARM_GCC_541\Debug\app-event.o .\CortexM0\ARM_GCC_541\Debug\app-time.o .\CortexM0\ARM_GCC_541\Debug\app-wdt.o .\CortexM0\ARM_GCC_541\Debug\app-led-btn.o .\CortexM0\ARM_GCC_541\Debug\app-statemanager.o .\CortexM0\ARM_GCC_541\Debug\debug.o .\CortexM0\ARM_GCC_541\Debug\TinyEncrypt.o .\CortexM0\ARM_GCC_541\Debug\app-sd.o .\CortexM0\ARM_GCC_541\Debug\ff.o .\CortexM0\ARM_GCC_541\Debug\rtc.o .\CortexM0\ARM_GCC_541\Debug\sdcard.o .\CortexM0\ARM_GCC_541\Debug\cyfitter_cfg.o .\CortexM0\ARM_GCC_541\Debug\cybootloader.o .\CortexM0\ARM_GCC_541\Debug\cymetadata.o .\CortexM0\ARM_GCC_541\Debug\Cm0Start.o .\CortexM0\ARM_GCC_541\Debug\PowerReader_application.a -mcpu=cortex-m0 -mthumb -L Generated_Source\PSoC4 -Wl,-Map,.\CortexM0\ARM_GCC_541\Debug/PowerReader_application.map -T .\LinkerScripts\cm0gcc.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -Og -ffat-lto-objects -Wl,--end-group
ERROR: CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.
collect2.exe: error: ld returned 1 exit status
The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
--------------- Build Failed: 10/01/2020 12:13:38 ---------------
Can anyone here help me to understand first what I did wrong, and how can I solve this problem ? It seems tpo me that this should all be configured through the GUI in TopDesign.cysch, as the linker script is overwritten during the build process, but I might miss something.
Thanx in advance !
Best regards
Eric
Show LessDear Sirs and Madams,
We are using the I2CHW Slave component of PSoC4S.
I2C Master and I2C communication is not working properly.
(a)
I2C HW component version : v40
I2C Address : 8
Data rate : 100kbps
I2C Master : Other CPU on the host side
This is the waveform at the time of Master transmission.
The slave does not return an ACK.
Waveform when I2C Master is changed to PC emulator and tried
(b)
I2C HW component version : v40
I2C Address : 8
Data rate : 100kbps
I2C Master : PC emulator
Delayed fall of ACK, delayed SCL.
However, the communication is successful.
Continuing from the continuous waveform above,
An ACK is output immediately on the data line.
Is there something wrong with the usage of I2CHW in PSoC4S?
"Byte mode”, "Accept General call address", "Enable wakeup from Deep Sleep Mode" are not checked.
Do you know how to get around this problem?
Regards,
Show LessHi,
I have a comparitor set up to monitor overcurrent in a motor drive application. The setup takes a reference voltage from an IDAC in the negative and has the current monitor voltage in the positive terminal. The ISR is firing when the + input is way too low. I have measured both voltages and confirmed that the ISR trips when the - input is about 20mV and the + input is around 2mV. Any ideas what is going on here? The calculations for the conditions back up the measurement.
The 10x difference made me think I missed something, but I remeasured the input voltages a few times, and that seems to be the difference when it trips.
Thanks in advance for any help!
Regards,
Tom