PSoC 4 MCU

Dear community members,

We use the PWM component with a downstream RC circuit in our design to achieve a clean analog voltage of 0-5V. Unfortunately, voltage drops occur sporadically. A CYBLE-214015-01 32-SMT is used in the design. The problem does not occur with every module either. The pins are all loaded with 180 kilohms.
All inputs on the CYBLE are wired as recommended with the corresponding inductances.
I am grateful for any help.

Daniel

Hello , 

I am trying to send my  data from the encoder to my cy8ckit-043 to check for any errors along with my CRC polynomial. How do I set it up in my PSoC creator. I made a CRC table in PSoc and wrote my polynomial representation too. I am still confused how to check for crc .  I would like to know about the seed value and my polynomial value, what do they generate? How should I send my data stream through di pin on crc?

Hi,

It says in PSoC Creator 4.4 under [Design Wide Resources > System] that

"Controls whether or not to reserve pins for debugging. If SWD is selected, the debugging features of the chip will be externally accessible. If GPIO is selected the pins are available for general purpose use. When set to GPIO the device can still be acquired with SWD, and reprogrammed, but not for debugging."

Does this mean that I can still program my CYBLE-214015-01 module with the P0[7] and P0[6] and subsequently use the SCB as SPI on these pins?

Hi,

We want to get below digital circuit running in deep sleep using LFCLK.

Is it possible to do that? Document shows  it is not is there any workaround to get running this functionality in <8uA.

If not possible, Is there any ICs available to implement such logic with low power?

Any suggestions?  we want to match bit pattern and wake up MCU on that event.

Regards,

Hardik Harpal

Hi. @MotooTanaka @BragadeeshV 

How can i use one capsense button with two event . Example if i am pressing capsense for 5 sec it will work for event number 2 @

Environment: PSoC Creator 4.4, CY8C4147AZI-S465

I'm going into the infinite IntDefaultHandler and seeing ENOMEM when calling srand() or rand() without heap.

Since I'm currently not doing any other dynamic memory allocation if I run the same code without calls to srand() and rand() the code runs fine, even without any heap.

Is it expected per the C standard?

I tried to run the exact same test of running srand() and rand() without heap on a TI F28002x and it runs fine, although of course rand() isn't actually returning a random number.

My fear is that srand() and rand() are unsafely using the heap in PSoC 4's implementation.

Hello,

The capsense slider of the CY8CKIT-149 is implemented with a Tx  pin , which is required in the  mutual capacitive sensing (CSX) mode. On the PCB design, the TX trace is distributed between every segment.  So hardware is OK for a slider in CSX mode. However when I checked in the "CE220891_CapSense_with_breathing_LED" project with PSCOC Creator, there is no other choice but CSD (self capacitance) for slider. 

I don't understand.Is it possible to configure slide in CSX mode? If no, why is the CY8CKIT-149  hardware implemented for It?

Best Regards

Until recently the dongle was working quite happily but now something seems to have happened to it.

When plugged in to the computer it isn't recognised as a COM device any more, Windows 10 treats it as an external drive and under Device Manager it appears as another drive, not a COM device.

I have updated the Firmware using CySmart 1.3, but when I try and upload the HEX file ( \\ \\ \\BLE_4_2_Dongle_CySmart_256K_psoc.hex using Programmer 3.29.1) I get the error that the PSoc device is not acquired.....

The red light is on and the green status light fades on and off rather than blinking.

I have tried all that I can find and got nowhere so I'm wondering if it is beyond repair.  Anyone else been here or have any ideas?

(I have another dongle on order so this isn't life and death, but it is bugging me.)

Many thanks

Andy

Dear Sirs and Madams,

We are considering using WDT  function for PSoC4S.

I set the "Timer (WDT)" on the "Configure System Clock" screen as shown below.

So we have some questions.

(1)

Is it necessary to set the "WDT_MATCH" register in the program even if the above settings are made in the GUI?

(a) No WDT_MATCH setting *IGNORE BIT(19-16bit) 3H

Probably the above is the initial value.

(b) With WDT_MATCH setting (set 1FFFH(8191D)) *IGNORE BIT(19-16bit) 3H

(2)

Even if you set the WDT on the GUI, if the WDT_MATCH register setting process is required in the program of main.c, zWe don't know the reason for setting "Period" on the GUI.

(3)

When will the WDT count start?

Is it the timing when the CySysWdtEnable API is called in PSoC4S?

Are there any other conditions for the WDT count to start?

Regards,

Hello,

We can see reports of radiated emissions in CapSense on AN64846 and AN85951.

Generally, the emission should be large at odd-numbered harmonics of the switching frequency, but from this figure, it seems that it is maximum at 24 MHz, which is an even-numbered harmonic. Why?

Best regards,

Yocchi