PSoC™ 4 Forum Discussions
Via firmware we can route any GPIOs to the ADC via analog switches inside the PSoC.
The TRM mentions the below text.
The additional switches reduce the scanning performance (more parasitic coupling, longer RC time to settle) – it is not fast enough to sample at 1 Msps. This is not recommended for external signals; the dedicated SARMUX port should be used, if possible.
But lets assume we need to mux ALL gpio's available into the ADC.
How can we calculate the maximum speed we can achieve. i.e. max adc sampling speed / (number of gpios * muxing, settling time, etc)!?
reference: Re: Which PSoC has the highest ADC input count (muxed)
Show LessI have a project I want to program to the microcontroller. When I try to upload the project to the microcontroller in PSoC creator it does not appear to be connected. However, I have it plugged in and the status LED is green and the power LED is on. How can I get PSoC creator to see the microcontroller?
Show LessHello, I am new to cypress. I was wondering if the KitProg 2 from the CY8CKIT-146 PSOC® 4200DS PROTOTYPING KIT can upload a BLE code to a PSoC 4 chip?
Show LessHi.
My customer use CapSense.
My customer wants a liquid tolerance layout in one layer.
So I thought about the layout as shown below.
The guard sensor will be cut off in order to realize it with one layer.
Is the function of the guard sensor maintained even in this case?
I would appreciate any other advice on layout.
Best Regards.
Show LessI've working I2C communication from my PSoC 4 as I2C master, with si1153 proximity sensor as slave, however I'm polling in main loop for a flag that will be set on falling edge from slave device specific pin. If this flag is set, I'm doing a block read.
If I try to perform the block read directly from the pin ISR, no I2C communication is performed? I would like to have ISR triggered I2C read method without the need for polling to be as fast as possible, how can I achieve this?
This doesn't do anything:
Show LessCY_ISR(btn_prox_isr_Handler)
{
uint8_t buffer[13];
Si115xBlockRead(0, SI115x_REG_IRQ_STATUS, 13, buffer);
prox_int_btn_ClearInterrupt();
}
Hi All,
I’ve been trying to better understand the Cypress operation based on a certain scenarios but have not had any luck getting a solid answer from the BLE datasheets and cypress BLE functions
What I am trying to do is get a better understanding of how communication between bonded appliances changes based on one or the other losing its bonding info
Scenario 1) Two bonded Cypress appliances, the central has its bonding list cleared
Scenario 2) Two bonded Cypress appliances, the peripheral has its bonding list cleared
I understand that the BLE stack handles this operation for us but I want to better understand how it handles edge cases.
That why I want to know how the two appliances determine that both have the necessary bonding information and what happens when this communication results in the Master or the Slave discovering that the other does not have the same information.
I can see that the GAP functions associated with the process but checking the contents of the functions does not give much info on what is actually happening behind the scenes.
CYBLE_EVT_GAP_AUTH_COMPLETE,
The event parameter contains the security information as defined by CYBLE_GAP_AUTH_INFO_T.
This event is generated at the end of the following three operations:
* Authentication is initiated with a newly connected device
* Encryption is initiated with a connected device that is already bonded
* Re-Encryption is initiated with a connected device with link already encrypted
During encryption/re-encryption, the Encryption Information exchanged during the pairing process
is used to encrypt/re-encrypt the link. As this does not modify any of the authentication
parameters with which the devices were paired, this event is generated with NULL event data
and the result of the encryption operation. */
Thanks in advance.
Show LessHi Everyone. I have an issue with Emulated EEPROM Component Versioned 2.20 in my PSoC4 Prototyping kit.
I have gone through the datasheet of Emulated EEPROM Component Version 2.20 and I have followed all the steps listed to set up fixed location based EEPROM in my PSoC4. While editing the linker script file "cm0gcc.ld" copy (custom_cm0gcc.ld), the key point is finding the line
.cy_checksum_exclude : { KEEP(*(.cy_checksum_exclude)) } >rom
in the code and adding the code segment
EM_EEPROM_START_ADDRESS = <EEPROM Address>;
.my_emulated_eeprom EM_EEPROM_START_ADDRESS :
{
KEEP(*(.my_emulated_eeprom))
} >rom
below it. I can not find the line in the linker file anywhere. What can be the reason behind this and how to resolve it? Attached herewith is my project and linker file.
Regards
Shaunak Vyas
Show LessHello,
Some years ago I've used CYBLE-012011-00 to developed a product after more than 10k units sold I'm facing a problem with new units.
The same module same board doesn't work with some new smartphones such as Samsung A51 or Samsung A20e!
but your other module CYBLE-014008-00 works just fine with all the devices!
Or even your new PSOC6!
I'm sure it isn't an SW issue because I've already tried with your BLE Find Me example in all these devices to be sure the code was the same etc.
This is a huge problem since I've thousands of units produced but they don't work on clients' phones!
I've pictures and videos that prove it but I can share with the Cypress team but only in a private way due to confidentiality!
Kindly ask you for attention on this matter,
Yours sincerely,
Carlos
Show LessI have an SPI slave set up on a CY8C4125AZI-473 and I am seeing some very odd behavior in both the setup controls and the SPI is not sending or receiving data. The project bundle is attached. When configuring, the dialog defaults to the one internal interrupt unchangeable, and I do receive the interrupt, but never receive any data, nor send any data.
The scope plot show the transmission, from a CYBLE-212006-01, 16bytes, 0,0, active low CS. We have also tried active high, but no change.
Sending an array of A5 5A, which should be echoed back by hard code, I am not trying to hand data off, the transmit should be getting the same array, here is the call that loads the TX buffer:
SPIS_SpiUartPutArray(Readings,CONTROL_DATA_LEN);
We have scoped the MOSI, CLOCK and SS to the pins on the device and the signals are present.
There is also a second SPI in the design, which works, but generates an error during build, that must be handled, but it should not be there. It is a Master that talks to a dedicated peripheral, when configuring that SPI, the dialog allows no interrupts:
But when you do a build, these instructions are in the generated source code, and have to be commented out on each clean and build
Map,.\CortexM0\ARM_GCC_541\Debug/EPR0226_Power_Control.map -T Generated_Source\PSoC4\cm0gcc.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -O0 -ffat-lto-objects -Wl,--end-group
.\CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearRxBuffer':
C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:205: undefined reference to `SPI_TLE_DisableInt'
C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:224: undefined reference to `SPI_TLE_EnableInt'
.\CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearTxBuffer':
C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:422: undefined reference to `SPI_TLE_DisableInt'
C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:432: undefined reference to `SPI_TLE_EnableInt'
Show LessI couldn't find an overview for this, I could of course check the datasheets 🙂 but assuming someone @ cypress has this info!
I need as many ADC inputs as I can get, 8-12bits input is ok and can be fairly slow / muxed.
Preferably from the PSoC 4000S, 4100S, 4100S Plus range (as supported by modus)
Show Less