PSoC™ 4 Forum Discussions
Environment: PSoC Creator 4.4, CY8C4147AZI-S465
I'm going into the infinite IntDefaultHandler and seeing ENOMEM when calling srand() or rand() without heap.
Since I'm currently not doing any other dynamic memory allocation if I run the same code without calls to srand() and rand() the code runs fine, even without any heap.
Is it expected per the C standard?
I tried to run the exact same test of running srand() and rand() without heap on a TI F28002x and it runs fine, although of course rand() isn't actually returning a random number.
My fear is that srand() and rand() are unsafely using the heap in PSoC 4's implementation.
hello,I‘m user of CY8C4014LQI-421_16-QFN. I have two questions about it .
- about the power supply mode.
"There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to 1.89, internal regulator bypassed)."
I want to know that which mode has stronger robustness?If I use the mode 2,what the pitfalls might it has?
- about the I2C
If I power the VDD=3.3V .what the high threshold and low threshold are?
3.3V*0.7and3.3V*0.3?
OR 1.8V*0.7and1.8V*0.3?
thanks!
Show LessHello,
The capsense slider of the CY8CKIT-149 is implemented with a Tx pin , which is required in the mutual capacitive sensing (CSX) mode. On the PCB design, the TX trace is distributed between every segment. So hardware is OK for a slider in CSX mode. However when I checked in the "CE220891_CapSense_with_breathing_LED" project with PSCOC Creator, there is no other choice but CSD (self capacitance) for slider.
I don't understand.Is it possible to configure slide in CSX mode? If no, why is the CY8CKIT-149 hardware implemented for It?
Best Regards
Show LessHello!
In the process of studying Bootloader\Bootladable projects, I noticed that bootloadable link script can improved (I thin so).
Original part is:
...
.bootloader_data (NOLOAD) : ALIGN(8)
{
. += BOOTLOADER_RAM_SIZE
}
...
Supposed improvement:
.bootloader_data (NOLOAD) : ALIGN(8)
{
. = BOOTLOADER_RAM_SIZE - SIZEOF(.ramvectors) - SIZEOF(.btldr_run);
}
As a result we can remove the memory leak of ~ 200 bytes.
Or may be I 'm wrong?
Thanks.
Show LessHello,
I am implementing a slider design following the "AN85951 PsoC4 and PSoC6 MCU CapSense Design Guide".
On the CYC8CKIT-PSOC149 development kit , buttons and slider are covered by solder mask, copper is coated. Hower it is not mentioned in "AN85951 PsoC4 and PSoC6 MCU CapSense Design Guide" that copper should be covered by solder mask.
Is it required to cover copper with solder mask? If so then what is the consequence on the capacity sensor?
Best Regards
Show Less
Dear Sirs and Madams,
We are considering using WDT function for PSoC4S.
I set the "Timer (WDT)" on the "Configure System Clock" screen as shown below.
So we have some questions.
(1)
Is it necessary to set the "WDT_MATCH" register in the program even if the above settings are made in the GUI?
(a) No WDT_MATCH setting *IGNORE BIT(19-16bit) 3H
Probably the above is the initial value.
(b) With WDT_MATCH setting (set 1FFFH(8191D)) *IGNORE BIT(19-16bit) 3H
(2)
Even if you set the WDT on the GUI, if the WDT_MATCH register setting process is required in the program of main.c, zWe don't know the reason for setting "Period" on the GUI.
(3)
When will the WDT count start?
Is it the timing when the CySysWdtEnable API is called in PSoC4S?
Are there any other conditions for the WDT count to start?
Regards,
Show Less
Hello ,
I am trying to send my data from the encoder to my cy8ckit-043 to check for any errors along with my CRC polynomial. How do I set it up in my PSoC creator. I made a CRC table in PSoc and wrote my polynomial representation too. I am still confused how to check for crc . I would like to know about the seed value and my polynomial value, what do they generate? How should I send my data stream through di pin on crc?
Show LessDear community members,
We use the PWM component with a downstream RC circuit in our design to achieve a clean analog voltage of 0-5V. Unfortunately, voltage drops occur sporadically. A CYBLE-214015-01 32-SMT is used in the design. The problem does not occur with every module either. The pins are all loaded with 180 kilohms.
All inputs on the CYBLE are wired as recommended with the corresponding inductances.
I am grateful for any help.
Daniel
Show LessHi,
We want to get below digital circuit running in deep sleep using LFCLK.
Is it possible to do that? Document shows it is not is there any workaround to get running this functionality in <8uA.
If not possible, Is there any ICs available to implement such logic with low power?
Any suggestions? we want to match bit pattern and wake up MCU on that event.
Regards,
Hardik Harpal
Show LessHello,
We can see reports of radiated emissions in CapSense on AN64846 and AN85951.
Generally, the emission should be large at odd-numbered harmonics of the switching frequency, but from this figure, it seems that it is maximum at 24 MHz, which is an even-numbered harmonic. Why?
Best regards,
Yocchi
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