Which MCU/PSOC should I use to implement LIN Master?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
PeterHirt
Level 1
Level 1
5 sign-ins First reply posted First question asked

Hello there!

I spent days trying to find the best solution for LIN Master without any luck.

The only chance to stay on Cypress (my favorite vendor) and not to migrate to Renesas is to get answer from you.

Help me!

0 Likes
1 Solution
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi @PeterHirt ,

The PSoC's internal clock can not fulfill the clock accuracy requirements for the LIN master as specified in the LIN spec. 

If you are looking for LIN master in industrial part, we recommend you to check out our XMC1000 and XMC4000 family of devices that support LIN master mode.  The XMC related queries are handled here. Please drop a question in the XMC forum if you have further questions.

Regards,
Bragadeesh

View solution in original post

0 Likes
7 Replies
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi @PeterHirt , Can you please confirm if you are looking for an automotive part or industrial part for your application. The PSoC 4 devices supports LIN over the UART protocol using the LIN component. This LIN component doesn't support LIN master. However, you can implement LIN master on top of the UART protocol in firmware using PSoC devices. We do not officially support this feature.

If you are looking for automotive parts, please check the Traveo-II devices which supports LIN master.

Regards,
Bragadeesh
0 Likes

Hello, @BragadeeshV !

The part I am looking for have to be an Industrial grade MCU.

What is the reason that Cypress doesn't have LIN-Master block?

Does Infineon have?

0 Likes
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi @PeterHirt ,

The PSoC's internal clock can not fulfill the clock accuracy requirements for the LIN master as specified in the LIN spec. 

If you are looking for LIN master in industrial part, we recommend you to check out our XMC1000 and XMC4000 family of devices that support LIN master mode.  The XMC related queries are handled here. Please drop a question in the XMC forum if you have further questions.

Regards,
Bragadeesh
0 Likes

Hi, @BragadeeshV 

XM1400 looks suitable!

Thanks!

0 Likes

Bragadeesh,

A LIN master requires +/- 0.5%.

Yes the internal clock has insufficient accuracy.   However using a crystal with the ECO should be achievable.

 

Len
"Engineering is an Art. The Art of Compromise."
0 Likes

Hi, @Len_CONSULTRON 

So it is possible eventually.

Maybe you can suggest some examples or provide any clues on how to make LIN Master in PSOC. I would like to use hardware blocks as much as possible?

0 Likes
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Peter,

I cannot find any Cypress examples of LIN Master implementations.  I have found LIN slave examples.

How familiar are you with the LIN specification?

You can find the full (unofficial) LIN spec on the web.   Cypress even provides some LIN specification info :  

Cypress LIN info 

I have created LIN slaves on other processors.  It's fairly easy.   In the early days of LIN, it was intended to be used with simple UARTs.   The only real difficult part of the spec regarding the UART was implementing the 13-bit Break pulse.  In the early days the break pulse implemented in SW.   Nowadays it is implemented in HW.

... use hardware blocks as much as possible ...

The LIN specification doesn't really allow for creating much of a hardware state machine.  Beyond the UART HW, you may be able to program DMA to send or receive data.   The tricky part is validating the LIN data with the checksum presented at the end of a LIN packet.  It's easiest done in SW.

Here's a quick summary of the LIN protocol at the highest level:

  • There can only be one LIN Master but you can have up to 32 Slaves.
  • No Slave can initiate a LIN packet.
  • Only the Master can initiate a LIN packet.
  • Only the Master can present the Break, Sync and PID portion of the serial data.
  • The PID value determines the type of data commanded or requested from a single Slave by the Master.
  • The PID values are predetermined at design-time.
  • If the PID is a data command, then the Master holds on to the LIN bus for the entire packet and presents the data to ALL the Slaves.  The data is only supposed to be used by the intended Slaves.
  • If the PID is a data request:
    • the Master must relinquish the LIN bus and go into read mode.
    • intended Slave must decode the PID and start placing the requested data on the LIN bus within a very short amount of time.
    • Once all the data from the Slave is transmitted (up to 8 bytes), the Slave relinquished drive control of the LIN bus back to the Master.

Once you meet the timing accuracy requirements (+/- 0.5%) using a crystal, the LIN Master is IMHO many ways simpler to implement. 

It is common for the Master to create one or more schedule tables.  Each schedule table is the sequence of LIN packets usually repeated in a cycle or in some cases the table is occasionally called to respond to an exceptional condition.

The main schedule table is the table that usually gets implemented the most.  It is comprised of continuously issued command PIDs with some Slave status data request PIDs determine the health of the Slaves.

Note:  You might find some good LIN Master scheduler source code for other processors that might be adapted.

I hope this is a good starting point.

Len
"Engineering is an Art. The Art of Compromise."