You would have multiple possibilities for implementation:
1. Knowing your clock frequency, you might be able to have a fixed instruction list in ASM that would run the bit sequence you desire for each 24-bit number you want to write, but it would be pretty difficult like you say. Setting the clock to 48-MHz will give 20.833 ns per instruction, which with a tolerance of +/- 150 ns on the datasheet, you would have a tolerance of about 6 or 7 assembly instructions, which should be plenty if you are doing a fixed assembly routine for each number.
Something along the lines of:
void SendNumber(void) {
//send a zero
CyPins_SetPin(LED_0);
CyDelayCycles(16);//16 cycles is about .35 us at 48 MHz
CyPins_ClearPin(LED_0);
//send a one
CyPins_SetPin(LED_0);
CyDelayCycles(43);//43.2 cycles is .9 us at 48 MHz
CyPins_ClearPin(LED_0);
//..... repeat sequence for multiple bits
}
//If the bits do not have to be consecutive as far as timing, then you only need a routine for bit 0 and bit 1
2. Since you would have 300 ns of time to finish each bit, you could theoretically use ISRs depending on how well you could implement 1 or 2 ISRs, whether you could switch the ISR timeout each time it is called, how many numbers you have to manipulate in assembly for each call, how long it takes the CPU to assert the ISR, etc.
3. You could use the TCPWM hardware to do the timing with a single PWM pulse, but it would only work if you have time to invert the PWM signal for each inverted bit (bit 1 versus bit 0) and can disable the PWM after 24 bits have been sent.
It all depends on how stringent your computing resources are on the chip, how much of the RGB functionality you want/need, and how much space you are willing to sacrifice for the RGB control.
