Vref in DeepSleep

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jedac_2823961
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Hey All,

In a design I've built I use the Vref bypass (see below) pin on 1[7] to do some safety checks with NTC's etc, because want to use the 1.024V.

pastedImage_0.png

When I started testing with DeepSleep mode I found out the ADC is shutdown, and also then the 1.024V on 1[7].

Does anyone know a good method to keep a voltage of 1.024 on a pin in DeepSleep?(I already tried using an IDAC to generate a current but that isn't that stable)

Or is there maybe a way to use Pin 1[7] for both the 1.024V of the ADC and as a GPIO that I can drive high(just for DeepSleep)

Hopefully the problem/question is clear enough!

-Jeroen

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RyanZhao
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250 sign-ins First question asked 750 replies posted

Hi Jeroen,

As you can see in PSoC 4 Low-Power Modes and Power Reduction Techniques https://www.cypress.com/file/121271/download ,

ADC is OFF in Deep Sleep mode.

The way to use Pin 1[7] for Vref and ADC, the KBA may be a reference on changing GPIO pin internal connection dynamically:

Controlling UART Tx and Rx Pins through Firmware for PSoC 4 Devices - KBA 224950

Thanks,

Ryan

View solution in original post

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RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Jeroen,

As you can see in PSoC 4 Low-Power Modes and Power Reduction Techniques https://www.cypress.com/file/121271/download ,

ADC is OFF in Deep Sleep mode.

The way to use Pin 1[7] for Vref and ADC, the KBA may be a reference on changing GPIO pin internal connection dynamically:

Controlling UART Tx and Rx Pins through Firmware for PSoC 4 Devices - KBA 224950

Thanks,

Ryan

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