I want to align two clocks running at 100KHz and 1MHz.
1. I declared a Design wide cock running at 1MHz
2. Then dragged and dropped two clock components in the top design.
3. Configured the source of one clock from "EXISTING" 1MHz design wide clock and for the other I used a new divider but the same design wide clock running at 1MHz.
The clock configured from "existing" design wide clock simply does not work.
I tried Bobs idea, used a divider on a 24 Mhz HFCLK, but PSOC 4 does not have phase align
feature, so 100 Khz clk started up 300 nS + from the 1 Mhz + edge. So that approach maybe
I came across this blog on Cypress website. It clearly explains how to synchronize two clocks on PSOC 4. I tried it, but didn't work for me.
Here is the link:
May be this could help or perhaps I am missing out something.