Good morning, I need to manage a serial interface using a sort of CSMA/CD detection feature at single bit level. All devices are master and stop thier transmission every time a collision is detected: each master send and read back what is transmitted on the line. The low level on the bus detain priority. Is there any example or is it possibile to find a specific component to obtain this scope? Thank you
I could take in account CAN bus too, but I need to verify (also cost of the component). I was thinking instead to use the enable logic of Tx pin to stop transfer and using an internal IRQ timer sincronized with my transmission verify if the returned bit is equal to the transmitted one. Could be possible to modify a UART component to assolve this request?
I verified, the standard CAN bus has got a decoding scheme complitely different respect to the UART start+8data+parity+stop and impedance line requirements seems not be compliant with mine. Suppose I need to interface with an already existing device already using a UART with CSMA detection and I need to replicate this kind of interface also over a Cypress device: which solution do you suggest? Is it possible to generate an hardware internal logic to modify the UART component to assolve to this task?
Modifying an existing UART component will be the easiest way to go. However, you should be thorough with the component architecture. Hence, I request you to kindly refer to the PSoC Creator Component Author Guide. Meanwhile, we can wait to see if anybody else has a better solution.
Please, in your opinion, could be possible to modify an existing UART component using Verilog Internal component schematic or the new component must be built from the beginning? An approach could be to use and XNOR port logic between Rx and Tx signals to verify/compare if trasmission must be stopped because of a collision event and this check must be executed before the end of next bit transfer event.
Once created the new component, is it possible to import it into PSOC4000S PSOC4100S devices not supporting UDB internal blocks?
I believe that PSoC4000/4100 series do not support custom components. It has to be plain C code.
For which PSOC4 families custom component support is available? And what do you mean with " It has to be plain C code" ? I can't modify UART component for these devices?
For 4000/4100 devices Cypress allows only Cypress-supplied components. That means that one can only play around standard UART by using own C-code. No custom components allowed.
I believe that byte-by-byte transmission with verification of echo-byte can be accomplished in code.
I think it is not possible to solve issue using only software without external hradware logic because when Tx buffer register is loaded it can't be stopped at collision detection.
Although it depends on how fast the UART must be,
and how much CPU MIPS you can shell out for the task,
writing a software UART might be another option.
Note: I'm meaning that without using hardware component,
and using a couple of GPIOs.
Thank you to your answers, I replay to everybody:
I need to clarify if UART component set in SmartCard mode with Tx lost arbitration could be used for my request: is single bit collision event sampled at the middle of the transferred bit? In my case Uart Rx and Uart Tx are both connected to the same bus system for long distances communication where some line delay are present, instead I think SmartCard Uart mode is conceived for on board component communication using fullduplex communication.
To use SmartIO I find issue to drive internal signals using firmware because a direct control register component is not available on PSOC4100S devices.
All your suggestions could be valid but I'm not implementing a new communication but I only need to interface a new device to other devices already implementing an UART with CSMA collision avoidance, so I can't use a different solution instead of UART standard.
I think this could be the easiest solution but to manage single bit transfer directly using single GPIO without hadware usage it is an issue when application require concurrent other Isr interrupt execution. To use UART peripheral (or others) could lighten micro to do these tasks and in that direction I was looking for suggestions.
Another option could be to sample every tranferred bit-to-bit data using an input capture timer synchronized (at the middle of each bit) with outputting bit stream and when collision is detected to kill data transfer using an external logic port. However to do that I need to know when a new reception trigger (start bit interrupt detection) to be sure not to start a new trasmission when a reception is in progress (this information in my opinion is not available using PSOC UART component: I was thinking to use instead a GPIO edge detection interrupt to recognize start bit incoming but a spike over the communication line could be wrongly detected as a start of communication).
For an XOR(or XNOR) implementation between the Tx and Rx signals to detect collision, you can consider using the SmartIO block available in the PSoC4000S/4100S devices that you need to use.
Based on the XOR output, an interrupt can be generated and in the interrupt routine, the drive mode of the UART Tx pin can be changed to High-Z so that the rest of the bits(following a collision detection) are not transmitted out of the chip.
But the interrupt latency must be well under one bit period(or half bit period?) of UART so that the appropriate action on collision detection can be taken in time.
I'm trying to implement this solution using your suggest but I have an issue: on PSOC4100S devices not supporting control reg component is it possible to directly access internal signals by firmware code?
I found PSOC4 UART component can be configured in SmartCard Mode and so a Tx lost arbitration feature is enabled. The single bit check sampling to verify arbitration lost is done at the middle of the bit?
Can you please attach your project and let us know what the current issue it is that you are facing?
Just to mention (although i dont like I2C)
Another serial standard supporting some kind of arbitration is I2C in multi master mode.
Another interesting link regarding your "impedance line requirements" and CAN might be