SW porting problem CY8C4247LQI-BL473 to CY8C4248LQI-BL543

[mibrc_1338451]

We were encouraged by our supplier to make a move from CY8C4247LQI-BL473 (BLE 4.1, 128 kB) to CY8C4248LQI-BL543 (BLE 4.2, 256 kB) due to cost optimization (BLE 4.1 being deprecated).

When changing the device (MCU type) of the project to CY8C4248LQI-BL543 build failed:

"Error: cdf.M0005: CyDsFit aborted due to errors, please address all errors and rerun CyDsFit. (App=cydsfit)"

I isolated the problem to an output pin that is mapped to XTAL32I/XTAL32O pins which are also P6(0-1) digital pins. It seems strange to me since we are not using external oscilator and the project works on all 128 kB 4.1 BLE PROC BLE and PSOC BLE MCUs. Once I disable the output pin, project builds fine.

Is there some specific with the 256 kB 4.2 BLE PSOC MCUs compared to 128 kB 4.1 BLE that would cause the before mentioned problem (unable to use XTAL pins as GPIO)?

Toolchain configuration:

PSoC Creator  3.3 CP2 (3.3.0.7343)

BLE component version: MAJOR: 3; MINOR: 10

[GeonaP_26]

Unless low power mode is not used, user can configure P6.0, P6.1 pins as GPIO in CY8C4248LQI-BL543 as well.

I am unable to recreate the issue in latest PSoC Creator 4.2. Could you share the project to understand whether it is project specific?

[mibrc_1338451]

Hi,

thank you for your help. I have included a zipped project with archive. I have removed all of our .c sources since they are irrelevant to the problem.

If this is really a PSOC Creator 3.3 problem, which version would you recommend so we could still use the same peripheral component versions, especially BLE?

[GeonaP_26 · Accepted solution]

To summarize, unless low power mode is not used, user can configure P6.0, P6.1 pins as GPIO in CY8C4248LQI-BL543 as well.

The shared project is built successfully in PSoC Creator 4.2. It is recommended to use latest PSoC Creator and BLE component with defect fixes and enhancements.