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PSoC 4 MCU

HeGi_2497906
Contributor II

I have an SPI slave set up on a CY8C4125AZI-473 and I am seeing some very odd behavior in both the setup controls and the SPI is not sending or receiving data.  The project bundle is attached.  When configuring, the dialog defaults to the one internal interrupt unchangeable, and I do receive the interrupt, but never receive any data, nor send any data. 

The scope plot show the transmission, from a CYBLE-212006-01, 16bytes, 0,0, active low CS.  We have also tried active high, but no change.

Sending an array of A5 5A, which should be echoed back by hard code, I am not trying to hand data off, the transmit should be getting the same array, here is the call that loads the TX buffer:

SPIS_SpiUartPutArray(Readings,CONTROL_DATA_LEN);

RigolDS12.png

We have scoped the MOSI, CLOCK and SS to the pins on the device and the signals are present.

There is also a second SPI in the design, which works, but generates an error during build, that must be handled, but it should not be there.  It is a Master that talks to a dedicated peripheral, when configuring that SPI, the dialog allows no interrupts:

But when you do a build, these instructions are in the generated source code, and have to be commented out on each clean and build

Map,.\CortexM0\ARM_GCC_541\Debug/EPR0226_Power_Control.map -T Generated_Source\PSoC4\cm0gcc.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -O0 -ffat-lto-objects -Wl,--end-group

.\CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearRxBuffer':

C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:205: undefined reference to `SPI_TLE_DisableInt'

C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:224: undefined reference to `SPI_TLE_EnableInt'

.\CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearTxBuffer':

C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:422: undefined reference to `SPI_TLE_DisableInt'

C:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:432: undefined reference to `SPI_TLE_EnableInt'

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1 Solution
HeGi_2497906
Contributor II

Thanks for the reply, I went checking and found that the first transaction stopped after 8 bytes, my SW implementation is not allowing my 16 byte buffer.  I reduced the package to 8 bytes, and now get successful communications.  Which device can I upgrade into to get a full 16 byte buffer?

H

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8 Replies
BragadeeshV
Moderator
Moderator

Hi HeGi_2497906​,

When you set the Rx Buffer size to 16, then the internal ISR takes care of receiving 16 bytes from the FIFO to the software buffer. This should not be handled by the application. From your use case, you can simply make the FIFO size in the component to 8 (which is the hardware FIFO size). This allows you to use an external interrupt (which you are already doing). You can configure the interrupt  for RX FIFO not empty and move the bytes to the software buffer (same way you are doing now)

I do not understand the build error in the second SPI block, although I'm able to reproduce the issue at my end as well. Simply deleting and placing the component again resolved the issue at my end.

Regards,

Bragadeesh

Regards,
Bragadeesh
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HeGi_2497906
Contributor II

Thanks for the reply, I went checking and found that the first transaction stopped after 8 bytes, my SW implementation is not allowing my 16 byte buffer.  I reduced the package to 8 bytes, and now get successful communications.  Which device can I upgrade into to get a full 16 byte buffer?

H

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BragadeeshV
Moderator
Moderator

Hi HeGi_2497906​,

When you set FIFO depth to 8 bytes in the component, you can't wait until you received 16 bytes in the ISR as you are currently doing. After 8 bytes are received, the hardware RX FIFO will overflow. You have to read the bytes one by one each time the RX FIFO not empty ISR triggers. You might not actually required a 16 byte hardware buffer to do this. In the present implementation, you are stalling the code in the ISR, which is not recommended. You could implement something like below:

/

/global variable

uint8 i = 0;

uin8 data[16];

main()

{

for(;;)

{

     if(packt_received)

     {

     //Loopback this data

          packt_received = 0;

          SPI_SpiUartPutArray(data, sizeof(data))

    }

}

}

//SPI ISR

CY_ISR(SPI_ISR)

{

if((SPI_GetRxInterruptSourceMasked() & SCB_INTR_RX_NOT_EMPTY ) !=0)

{

while(SPIS_SpiUartGetRxBufferSize() != 0) //read whatever is there in FIFO until it reads 0

{

     data = SPI_SpiUartReadRxData();

     i++;

     if(i >15)

     {

          //transmission complete

           packt_received = 1;

          i = 0; //reset index

      }

}

SPI_ClearRxInterruptSource(SCB_INTR_RX_NOT_EMPTY);

}

}

Additionally, for devices  PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices, the RX and TX FIFO depth is equal to 8 bytes/words or 16 bytes. For these devices the component allows you to double the size of the hardware FIFO depth from 8 bytes/ words to 16 bytes.

Regards,

Bragadeesh

Regards,
Bragadeesh
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HeGi_2497906
Contributor II

I see that your are not waiting for the buffer to fill just taking the data until you get 16, but what I found was causing the issue what the transmission, even though I did a put array call with 16 bytes, the logic analyzer showed the TX stopping after 8 bytes, the dialog was set to 16. I will try 16 again, the way you are doing it, but when I increase the bytes to 16, the RX_BUT_NOT_EMPTY interrupt check box greys out but is checked, what does that mean?

RigolDS22.png

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HeGi_2497906
Contributor II

That did not work, data receive fails completely and the transmit has rolling errors, based on value 8, the hw buffer, what is going on?

I have to make 8 bytes work until we flush this out, but this is not functional at this point,

H

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BragadeeshV
Moderator
Moderator

Hi HeGi_2497906​,

I will try 16 again, the way you are doing it, but when I increase the bytes to 16, the RX_BUT_NOT_EMPTY interrupt check box greys out but is checked, what does that mean?

--> As I mentioned earlier, the hardware buffer size is only 8 bytes/ words. Therefore, when you set the buffer size as 16 in the component, we are using an internal ISR to manage data transfer from FIFO to the software buffer. Now, to do this, the software buffer needs to enable RX FIFO not empty interrupt. That is why this option is greyed out indicating that it is mandatory if you have set buffer size greater than 8 in the component.

What I found was causing the issue what the transmission, even though I did a put array call with 16 bytes, the logic analyzer showed the TX stopping after 8 bytes, the dialog was set to 16

-> SpiUartPutArray is a blocking function. It waits until it has space to put in the TX FIFO. Therefore the size of the array can be greater than the size of the hardware buffer. We should not be seeing any overflow errors.

Can you share your latest code with us?

Regards,

Bragadeesh

Regards,
Bragadeesh
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HeGi_2497906
Contributor II

Can you send an example that I can test for the 212006, it is not working at 16bytes, it hangs up on the PUT BUFFER instruction, and just waits there now?

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BragadeeshV
Moderator
Moderator

Hi HeGi_2497906​,,

Can you test the attached project? Let us know if it helps.

Regards,

Bragadeesh

Regards,
Bragadeesh
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