SPI Master reset using timer counter

[user_2457466]

Hi,

I am currently working on a system, where I transmit data using SPI master component. I ahve a counter connected. Which count SCLKs. After a certain number of bits have been clocked out, I want to halt the transmission using the component on the topdesign.

I have tried to use a basic count7 component and connected the tc output to the reset input of the SPI master component. But that did not work.

Does anyone know how this can be achieved ? What is the timing requirement for the reset input ?

To ensure no further bits are clockced, it needs to be fast and therefore SW intervention, may not be fast enough. Thats why i do not use interrupts.

[Hari · Accepted solution]

Hi @user_2457466 

The easiest way to achieve this is to configure the SCB so that it sends out only 7 bits 

But once the data is added to the SCB's FIFO, the hardware block sends the data out. Blocking or issuing a firmware disable will still take effect only after the byte is transmitted. 

Best regards, 
Hari