Regarding PSoC4S I2C interrupt

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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
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Customer evaluates PSoC4S(CY8C4045AZI) as CapSense and EZI2C.

They would like to control GPIO independent of CapSense Scan interval immediately after the host writes some PSoC register by I2C.

They would like to confirm that PSoC I2C register has been rewritten by using I2C interrupt.

Is there such sample code or project file of I2C interrupt?

Best Regards.

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1 Solution

Hi matsubara-y_1534086​,

Can you try using EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback() (if clock stretching is enabled) or  EZI2C_1_EZI2C_NO_STRETCH_ISR_ExitCallback(); (if clock stretching is not enabled). These functions are called immediately after the I2C_ISR and hence will not have much time delay. you need not poll the SCB_EZI2CGetActivity() then.

Define the macro in cyapicallbacks.h

#ifndef CYAPICALLBACKS_H

#define CYAPICALLBACKS_H

  

   #define EZI2C_1_EZI2C_STRETCH_ISR_EXIT_CALLBACK

   void EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback();

#endif /* CYAPICALLBACKS_H */ 

In main.c or any other project file,

void EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback()

{

    /*Processing*/

}

Regards,

Bragadeesh

Regards,
Bragadeesh

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BragadeeshV
Moderator
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First question asked 1000 replies posted 750 replies posted

Hello matsubara-y_1534086​,

Could you please provide the following information?

1.They would like to control GPIO independent of CapSense Scan interval immediately after the host writes some PSoC register by I2C.

Could you please elaborate this statement?

2. Do you want to generate interrupt whenever a byte is received?

3. They would like to confirm that PSoC I2C register has been rewritten by using I2C interrupt.

Could you please elaborate this statement?

Regards,

Bragadeesh

Regards,
Bragadeesh
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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Host writes PSoC I2C register at some timing.

Customer want to add PSoC processing(for example, GPIO toggle, etc) after PSoC I2C register has been written.(at every write timing from HOST)

They can check whether register has been rewritten by polling.

However, in polling, a delay occurs between write timing and PSoC processing.

So they are considering whether I2C interrupt can be used or not.

Best Regards.

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Dear matsubara-y_1534086​ -san,

Thanks for the update.

EZI2C is already interrupt driven. It works on interrupts only. So instead of polling the register, you can use the SCB_EzI2CGetActivity() API and check if the return value is SCB_EZI2C_STATUS_WRITEx. This means that the write transfer is complete and the buffer content was modified.  But, the error condition status bit must be checked to ensure that write transfer was completed successfully.

PSoC 4 SCB Component datasheet:

https://www.cypress.com/file/408071/download

Please let us know in case of further clarifications.

Regards,

Bragadeesh

Regards,
Bragadeesh
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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Dear Bragadeesh-san.

Thank you for your response.

I think that there will be time delay between timing that SCB_EzI2CGetActivity() is called and SCB_EZI2C_STATUS_WRITEx is set.

Customer want to add PSoC processing(for example, GPIO toggle, etc) immediately after(at the same timing as) PSoC I2C register has been written.(at every write timing from HOST).

Is there a way to realize this?

Is it difficult?

Best Regards.

Matsubara

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Hi matsubara-y_1534086​- san,

Thanks for the update. Could you please let us know the actual timing you require? Could you also measure the present timing difference you get with the present approach? Let me know the difference. The CB_EZI2C_STATUS_WRITEx bit would be set in a very negligible timing only.

Also with the present configuration, you may not able to achieve what you require using the EZI2C, you may have to modify the source files.

Regards,

Bragadeesh 

Regards,
Bragadeesh
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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Bragadeesh-san.

PSoC does not know when Host will rewrite PSoC’s register.

Therefore, even if user uses “SCB_EzI2CGetActivity()”, I think that user can only use of processing by polling.

There is no problem if “SCB_EzI2CGetActivity()” can be called by chance immediately after Host rewrites register.

But If “SCB_EzI2CGetActivity()” is called a few seconds after Host rewrites register, time delay will occur.

So I thought that there will be time delay between timing that SCB_EzI2CGetActivity() is called and SCB_EZI2C_STATUS_WRITEx is set.

Please advise it.

Best Regards.

Matsubara

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Hi matsubara-y_1534086​,

Can you try using EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback() (if clock stretching is enabled) or  EZI2C_1_EZI2C_NO_STRETCH_ISR_ExitCallback(); (if clock stretching is not enabled). These functions are called immediately after the I2C_ISR and hence will not have much time delay. you need not poll the SCB_EZI2CGetActivity() then.

Define the macro in cyapicallbacks.h

#ifndef CYAPICALLBACKS_H

#define CYAPICALLBACKS_H

  

   #define EZI2C_1_EZI2C_STRETCH_ISR_EXIT_CALLBACK

   void EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback();

#endif /* CYAPICALLBACKS_H */ 

In main.c or any other project file,

void EZI2C_1_EZI2C_STRETCH_ISR_ExitCallback()

{

    /*Processing*/

}

Regards,

Bragadeesh

Regards,
Bragadeesh
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