Regarding I2C Bus Clear

[YuMa_1534086]

Hello

When PSoC operates as I2C master, SDA is stuck LOW by reset etc.

I know that this issue is solved if PSoC sends clocks.

But I2C specification has the following description.

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If not, then use the HW reset or cycle power to clear the bus.

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Does this mean that sending clocks may not improve it?

If user definitely want to improve this problem, does they need to use the HW reset or cycle power?

Best Regards.

Yutaka Matsubara

[MotooTanaka · Accepted solution]

Hi,

As you have already posted "usually" sending forced clock fixes the problem,

https://community.cypress.com/t5/PSoC-4-MCU/Regarding-PSoC4-I2C-reset-for-I2C-slave-hang-up-SDA-is-l...

but in case the I2C component or IP of the slave is stack in unknown state and not monitoring the bus any more,

in other words, when I2C component of the slave is not functioning as I2C any more,

probably a hardware reset will be the last resort.

A few years ago,  in a POC project of sensor hub, I programmed something like below

when an I2C_Slave is not responding

send forced clock

if still it is not responding

restart whole system

moto

[YuMa_1534086]

Moto-san.

I posted this question because I saw a symptom that I2C communication did not improve even if I sent clocks.

SDA returned to HIGH but I2C communication has failed.

So I wanted to confirm whether only sending clocks could definitely solve this issue.

I would use the HW reset or cycle power to ensure that this issue is avoided.

Thank you for your response.

Best Regards.

Yutaka Matsubara