cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 4 MCU

Contributor

Hello Cypress.

Q1)

When Tx clock source setting is “Auto”, how does CSX select it?

Below is my understanding.

Is my understanding correct?

====================================================

1: Check whether both of following 2 relational formulas are satisfied.

     a) 20 =< ModCLK/TxCLK =< 160

     b) Nsub >= (2^sscn-1) * (ModCLK/TxCLK)

2: The Priority order is as follows.

     (Higher) SSC10 -> SSC9 -> SSC7 -> SSC6 -> Direct (Lower)

   (TX clock source setting becomes “Direct” if either a) or b) of above formulas is not satisfied.)

====================================================

Q2)

If Q1 is yes, Number of subconversion needs to be quite large value in order for SSC to be selected.

In actual application, I think that SSC almost is not selected.

Even if CSX Tx clock source setting is “Auto”, sense clock source will become “Direct” in most cases.

Is my understanding correct?

For example, if ModCLK is 24000kHz and TxCLK is 300kHz, SSCx is not selected regardless of value of subconversion.

SSC is difficult to choose, so CSX noise tolerance seems to be worse compared to CSD.

CSD’s SSC is also difficult to choose, but CSD has PRS.

Please advise it.

Do you have any information and comment about it?

Best Regards.

Yutaka Matsubara

0 Likes
Reply
1 Solution
Moderator
Moderator

Matsubara-san,

A1. Yes. Your understanding is correct.

A2. Yes. And it depends on the actual application. Once the application hardware finished, the clock choice under Auto is decided in most cases. Even with direct clock, the flat spots may not occur in 100%. Flat spots tend to occur with large Cm, CintA/B. And actually, even the clock mode select rule you mentioned in Q1) is not met,  we can select SSC clock in most cases. The signal amplitude could be smaller than expected in this case, but CapSense can works under the situation of Nsub < (2^sscn-1) * (ModCLK/TxCLK) .

Best Regards,

Ryan

View solution in original post

0 Likes
Reply
2 Replies
Moderator
Moderator

Matsubara-san,

A1. Yes. Your understanding is correct.

A2. Yes. And it depends on the actual application. Once the application hardware finished, the clock choice under Auto is decided in most cases. Even with direct clock, the flat spots may not occur in 100%. Flat spots tend to occur with large Cm, CintA/B. And actually, even the clock mode select rule you mentioned in Q1) is not met,  we can select SSC clock in most cases. The signal amplitude could be smaller than expected in this case, but CapSense can works under the situation of Nsub < (2^sscn-1) * (ModCLK/TxCLK) .

Best Regards,

Ryan

View solution in original post

0 Likes
Reply
Contributor

Ryan-san.

Thank you for your response.

I understand it.

Best Regards

Yutaka Matsubara

0 Likes
Reply