PSoC4S : UART (SCB) data capture timing

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Dear Sirs and Madams,

 

We are considering a PSoC4S UART (SCB) component. 

Therefore, we are verifying the problem due to the timing of UART communication.

 

The configuration of PSoC4S UART is as follows:

MaMi_1205306_0-1620785319189.png

 

One frame of UART communication is as follows:

MaMi_1205306_1-1620785395389.png

 

(1)

As in Expansion 1, the clock accuracy of PSoC 4S is +/- 2%.

Since one UART clock can have an error of 2%, there is a possibility that an error of 20% will occur in the final stop bit of 2% x 10 bits in 10 bits of one frame.

Is this perception correct?

 

(2)

As in Expansion 2, shows the relationship between RS-232C and PSoC4S master clock.

When the maximum error as in (1) is considered,

Do you know what number of the master clock the timing that PSoC4S takes the UART data into the register corresponds to?

 

Regards,

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1 Solution

MaMi,

The HW state machine of the UART resynchronizes to the falling edge of the start bit.   Once this falling edge occurs, the UART expects read the bit value in about the middle of the bit frame.  

Timing slippage occurs when the actual Tx baud is different from the Rx baud by about +/- 4%.

Here's a simulation I ran with the bit sampling pulse on the bottom plot and the EXACT baud desired on the top.  The middle two plots are the baud - 4% and the baud + 4%.  (Note:  The comm spec is 115.2Kbps,  9-bits and one parity bit)

Len_CONSULTRON_1-1621517584011.png

The simulation shows that there is virtually insignificant slippage in the first bits.  However the sampling slippage occurs worst at the last bits being sent (which is the parity).  Beyond +/-4% bit errors can occur.    An IMO with +/- 2% over the operational temp range should be OK.

If you prefer better tolerance you would need to implement a crystal using the PSoC's ECO.  This will give you better than 20 ppm (0.02%) tolerance.

Note:  There are some protocols that use the UART for communication that require much better tolerance specifications.

For example, LIN (also known in the US as SAE2602) requires the LIN master baud to have 0.5% tolerance.  However LIN slaves are allowed to have a 1.5% tolerance.

Len
"Engineering is an Art. The Art of Compromise."

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7 Replies
Hari
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi @MiNe_85951 

 

1. That is not probable as it is the IMO that has an inaccuracy of +/-2%. When it comes to the actual UART bits, the error will mostly average out and you can expect to see only a 2% error between the bits as well. The error is not compounded between the bits. 

 

2. I do not understand this, could you please explain this query? Once the 8 bits are received, it is stored in the UART FIFO directly. The PSoC has to initiate a software read of this FIFO to get the data. 

 

Best regards, 
Hari

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hari-san,

 

Thank you for your support.

1.

I am being asked to explain why errors are not added between bits.

 

2.

We understand that getting data from a UART FIFO calls a software API.
We were concerned about when the UART data was taken into the UART FIFO.

 
 
 
 
 

 

キャプチャ.PNG

Regards,

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

MaMi,

My experience with UART protocol is that the frequency difference between the Tx on one system and the Rx on the other system can be as high as +/-4%.   Any more than that, a single-byte error can occur.

In the UART Rx HW state machine, the beginning of the start bit is used to resync the bit recovery with a > 8 clock oversampling helping out.

Normally a +/- 4% variance can allow up to 1 stop bit, 8 data bits, 1 parity bit and 2stop bits. before getting out of sync.   Again the beginning of the start bit resyncs the HW state machine for the next byte.

Does this help?

Len
"Engineering is an Art. The Art of Compromise."
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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Len-san,

 

Your explanation was easy to understand and was very helpful.

However, I am being asked to explain why errors are not added between bits of UART.

 

Regards,

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Hari
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello @MiNe_85951 

 

The IMO errors average out over time. Note that there are many more IMO cycles between each bit of UART transmissions, so over the period of UART transmission, the errors will not compound and add to one big error.

 

Best regards, 
Hari

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hari-san,

 

You say that IMOs are averaged over time, but how are they averaged?

Also, as a result of averaging, will it converge to an error of +/- 2%?

Please tell us the details about the reason why it does not shift by +/- 2% on a regular basis.
Does this +/- 2% accuracy mean a jitter characteristic with an error of up to +/-2% in one clock cycle?

 

This is a very important discussion for us, so please answer.

 

Regards,

0 Likes

MaMi,

The HW state machine of the UART resynchronizes to the falling edge of the start bit.   Once this falling edge occurs, the UART expects read the bit value in about the middle of the bit frame.  

Timing slippage occurs when the actual Tx baud is different from the Rx baud by about +/- 4%.

Here's a simulation I ran with the bit sampling pulse on the bottom plot and the EXACT baud desired on the top.  The middle two plots are the baud - 4% and the baud + 4%.  (Note:  The comm spec is 115.2Kbps,  9-bits and one parity bit)

Len_CONSULTRON_1-1621517584011.png

The simulation shows that there is virtually insignificant slippage in the first bits.  However the sampling slippage occurs worst at the last bits being sent (which is the parity).  Beyond +/-4% bit errors can occur.    An IMO with +/- 2% over the operational temp range should be OK.

If you prefer better tolerance you would need to implement a crystal using the PSoC's ECO.  This will give you better than 20 ppm (0.02%) tolerance.

Note:  There are some protocols that use the UART for communication that require much better tolerance specifications.

For example, LIN (also known in the US as SAE2602) requires the LIN master baud to have 0.5% tolerance.  However LIN slaves are allowed to have a 1.5% tolerance.

Len
"Engineering is an Art. The Art of Compromise."