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PSoC 4 MCU

MaMi_1205306
Honored Contributor

Hi,

We are communicating using the UART(SCB) of PSoC4S.

The UART settings are as follows :

-- Mode:Standard

-- RX+TX

-- 19200bps(Actual 19231bps)

-- 8bit data length

-- Non parity

-- Stop bit 1

-- Oversampling 12

 

Therefore, we would like to detect two types of communication errors.

(1) Detection of parity bit of data transmitted to PSoC4S.

We understand that PSoC Creator enables Uart Advanced tab's RX parity error check when parity is present(Even/Odd).

However, it cannot be set when no parity is selected.

Is there a way to detect the value of the destination parity bit?

 

(2) Detection of different data lengths
When the reception setting of PSoC4S is 8bit data length, We would like to detect the case where the data sent from the destination is 7bit data length.

 

Regards,

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1 Solution
BiBi_1928986
Valued Contributor

Hello.

For (1), 
PSoC4S  8-bits [Non parity]  RX <= UART =   TX 7-bits+ [Odd/Even parity]
This will be received by PSoC4S without framing error.

For (2), yes.  If there is an idle of at least 1 bit time, between 7-N-1 data, a Stop bit is recognized and no framing error occurs.

View solution in original post

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7 Replies
ncbs
Moderator
Moderator

Hi @MaMi_1205306,

> When parity bit is not enabled, then the RX parity error check cannot be accessed/used. However, you may manually calculate the parity (even or odd) by reading the data present in the RX buffer in your application.

> SCB_UartGetByte(void); function may be used to retrieve the received byte, and the character variable which stores the return value can be examined for 7bit or 8bit data.

 

Regards,
Nikhil

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BiBi_1928986
Valued Contributor

Hello.

For (2), this is 7-N-1 format of bits.  So, the Stop bit from 7-N-1 would appear in the 8-N-1 receiver at the 8th data bit.  If two 7-N-1 characters are sent back-to-back, the second character Start bit from 7-N-1 would land in the 8-N-1 receiver at the 8-N-1 Stop bit position.  This would result in a framing error (along with subsequent data errors).

So, to receive 7 bit data, the format would need to be 7-N-2.  The 8-N-1 receiver would always see the 8th bit set to 1.  Not a robust way of detecting 7 bit data since it could be confused for 8 bit data.

I would say the real answer is, no, there is no method to detect 7 bit data when both ends are configured differently.  Not unless you wanted to bit-bash the serial data stream, analyze it to find Start-Stop bits always appearing in certain positions that defines 7-N-1 data stream.

Or, maybe I mis-understood your question.

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MaMi_1205306
Honored Contributor

Thank you for your reply!

 

For (1), 

PSoC4S  [Non parity]  RX <= UART =   TX [Odd/Even parity]

In the above case,

Since the PSoC4S UART is set to have non parity, I think it can read data regardless of the parity bit.

Is it possible to generate a framing error?

 

For (2),

PSoC4S  [8bit data length]  RX <= UART =   TX [7bit data length] 

7bit data is incremented and transferred.

In the above, I assumed a framing error, but no framing error has occurred.

 

Regards,

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MaMi_1205306
Honored Contributor

I modified the UART sample project and confirmed it with CY8CKIT-145.

Connect TeraTerm and CY8CKIT-145,
Regarding the serial port setting of TeraTerm, even if I changed the parity from Non to Odd or Even, the local echo was successful.
Similarly, even if the data length is changed from 8bit to 7bit, the local echo will be performed normally and the frame error interrupt will not occur.

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BiBi_1928986
Valued Contributor

Hello MaMi.

Simple character echo will work because there is sufficient idle time between characters.  This idle time looks like a Stop bit for the receiver.  You can verify this with oscilloscope (if you have access to one).

Try transferring a text file.  This will send characters back-to-back without producing idle time between characters.  If you do not observe framing errors, then something is wrong with UART configuration.

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MaMi_1205306
Honored Contributor

Hi,

Please answer my two questions if possible.

Regarding question (1), does PSoC4S not cause a framing error?
Regarding question (2), is it correct to understand that if there is an idle time between packets, it is regarded as a stop bit and no frame error occurs?

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BiBi_1928986
Valued Contributor

Hello.

For (1), 
PSoC4S  8-bits [Non parity]  RX <= UART =   TX 7-bits+ [Odd/Even parity]
This will be received by PSoC4S without framing error.

For (2), yes.  If there is an idle of at least 1 bit time, between 7-N-1 data, a Stop bit is recognized and no framing error occurs.

View solution in original post

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