PSoC4S : CY8C4126AXI-S443 : UART communication Odd/Even settings

[MiNe_85951]

Dear Sirs and Madams,

I asked a question before, but the problem has not been solved yet.

https://community.cypress.com/t5/PSoC-4-MCU/PSoC4S-CY8C4126AXI-S443-UART-communication-error-detecti...

Regarding the UART component of PSoC4S,

When PSoC4S is set to no parity, if data with parity is transmitted continuously, the data cannot be received normally frequently, resulting in a mismatch between the transmitted data and the received data.

So, I would like to ask you another question.

(1)

/* PSoC4 UART settings */

Mode : Standard

RX+TX

19200bps (Actual 19231bps)

8bit data length

Parity non

Stopbit 1

Oversampling 12

/*************************************/

If parity (odd / even) data is received with the above settings, Do you know how PSoC4 behaves when it receives parity (odd / even) data with the above settings?

In our system, PSoC4S may have problems not only "no parity error" but also "data cannot be received correctly".

The fact that PSoC4S cannot receive correctly means that the values of the transmitted data and the received data may differ.

(2)

I've heard that if PSoC4S is set to no parity, a parity error cannot be detected even if data with parity is received.
We thought that even if we received data with parity when no parity was set, we could receive the data normally. Can you understand the reason why the data cannot be received normally with PSoC4S?

(3)

Previously, I got the following answer.

Is it possible to provide a concrete application example?

/***********************************************************************************************************/

> When parity bit is not enabled, then the RX parity error check cannot be accessed/used. However, you may manually calculate the parity (even or odd) by reading the data present in the RX buffer in your application.

/***********************************************************************************************************/

Regards,

[BiBi_1928986 · Accepted solution]

Hello.

Try code example CE224406 SCB UART for your target PSoC.

CE224406 loaded on CY8C4245 runs with no errors using polling mode and interrupt mode.  CY8C4245 doesn't support DMA mode.

PSoC configured for 8-N-1.
PC configured for 8-N-1, no errors.
PC configured 7-P-1 (odd, even, mark,space) and no errors.

[MiNe_85951]

/***********************************************************/

PSoC configured for 8-N-1.
PC configured for 8-N-1, no errors.
PC configured 7-P-1 (odd, even, mark,space) and no errors.

/***********************************************************/

Is it okay to understand that PSOC4S was able to receive data normally in your above operation check?

Successful reception of data means that the data received by PSoC 4S matches the transmitted data.

[BiBi_1928986]

Yes, no errors using CY8C4245.  You have to run test on PSoC4S.

[Len_CONSULTRON]

MaMi,

Your best answer is if you know the communication specification of the Tx end, then it is best to match it on your Rx end (obviously).

If you don't know it then you can set the Rx end (PSoC4 UART) to receive 9 bits and NO PARITY setting.   This should prevent a PARITY ERROR show up.   However you might receive a FRAMING_ERROR due to the stop bit not being in the correct position.

With the 9 bits of data, you can programmatically calculate the parity in the 9th bit and determine if there is an error.