Hello,
I am connecting the PSoC CY8CKIT-042 board's SPI interface to a SPI master device, the HFCLK is 48Mhz, the SPI master clock is 8Mhz,
the PSoC 4 is SPI slave, the SPI works on Motorola mode, the SCLK mode is "CPHA = 1, CPOL= 1", in this configuration, the SPI master always receives wrong MISO data from PSoC 4200 chip.
After i measured the SPI signals by a logic analyzer, i found the SPI MISO signal had big lantency, the lantency is about 80-90ns which assert after next clock rising edge, so the SPI master can not launch correct MISO data.
Look at the datasheet of PSoC 4200, the following AC Specifications of SPI Slave Mode:
Spec ID Parameter Description Min Typ Max Units
SID171 TDSO MISO valid after Sclock driving edge – – 42 + 3 ×Tscbclk ns
By my understanding, this SID171 means the MISO lantency may be the maxium 104.5ns.
Is is correct for my case? Is the PSoC 4 SPI slave not possible to get working on 8Mhz clock?
Thanks,
-Charlie
