I am connecting the PSoC CY8CKIT-042 board's SPI interface to a SPI master device, the HFCLK is 48Mhz, the SPI master clock is 8Mhz,
the PSoC 4 is SPI slave, the SPI works on Motorola mode, the SCLK mode is "CPHA = 1, CPOL= 1", in this configuration, the SPI master always receives wrong MISO data from PSoC 4200 chip.
After i measured the SPI signals by a logic analyzer, i found the SPI MISO signal had big lantency, the lantency is about 80-90ns which assert after next clock rising edge, so the SPI master can not launch correct MISO data.
Look at the datasheet of PSoC 4200, the following AC Specifications of SPI Slave Mode:
Spec ID Parameter Description Min Typ Max Units
SID171 TDSO MISO valid after Sclock driving edge – – 42 + 3 ×Tscbclk ns
By my understanding, this SID171 means the MISO lantency may be the maxium 104.5ns.
Is is correct for my case? Is the PSoC 4 SPI slave not possible to get working on 8Mhz clock?
Upload the picture of the logical analyzer, i draw two array to show the lantency form the SPI clock falling edge to the MISO assert.
Thanks your reply, but the Fspi is max 8Mhz according bellow AC specs for 4200，
what's different between the fsclk and this Fspi?
By the way, i can not get the fsclk in the 4200 datasheet.
The SPEC you attached, that is SPI slave by UDB, not the SCB's SPI, the two are different component and have different specs.
I am using SCB's SPI slave, i evaluate the SCB's SPI on a PSoC 4200 and will move to PSoC 4000S for a real project, because the PSoC 4000S do not have UDB SPI slave, i have to use SCB's SPI slave on my project.
I have to run SCB's SPI slave at 8Mhz frequency, this is critical for my project.
Would you please help to double check the issue? I hope there is a solution to fix it.
I would suggest you to get in contact with Cypress directly: At top of this page select "Design support -> Create a Support Case" and ask your question. You will be helped by a Cypress engineer.
OK, thanks your suggestion.
BTW, i misunderstood that you are in Cypress because you often answer questions in this forum. 🙂
Please see the image attached. This shows how the frequency is calculated. When you substitute parameters corresponding to your circuit you will get a lesser value. This can be found in the SPI component datasheet(right click on component-> datasheet) slave rate calculations section. You can see what each of the parameters mean. If your master supports MISO late sampling, that may solve your issue.
Thanks your reply, your point is clear, i were not aware that.
But unfortunately, the master does not supports MISO late sampling.
BTW: the PSoC4's SPI data rate is slow than the STM32, the STM32 can get above 10Mbps data rate at same configuration.