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chwa_1570756
Level 4
Level 4
25 sign-ins 25 replies posted 10 replies posted

Hello,

I use SPI as master and enable the interrupt of RX FIFO not empty, the code and setting are listed below.

In slave end, I did not write any data to slave FIFO buffer and even I physically terminate SPI connection.

My problem is why once excuting the line of SPIM_SpiUartPutArray(TxBuff,5), the system always enter into

Master_ISR.

Chris

void Master_ISR()

{

    SPIM_SpiUartClearRxBuffer();  

    SPIM_ClearRxInterruptSource(SPIM_INTR_RX_NOT_EMPTY);  

}

int main(void)

{

    uint8 TxBuff[5] = {1,2,3,4,5};

    SPIM_Start();

    SPIM_SetCustomInterruptHandler(*Master_ISR);

    CyGlobalIntEnable;

   

    for(;;)

    {

        SPIM_SpiUartPutArray(TxBuff,5);

    }

}

pastedImage_1.png

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1 Solution

Hi Chris,

This is expected behavior only. In case of SPI the Master doesn't wait for acknowledgement from the slave to transfer or receive data.

Upon Master write, the master simply enables the Slave select line and sends the data( drives MOSI) and reads MISO. When there is no slave, the master will read the data as 00 on the MISO. The developer has to do implement mechanism to avoid this issue.

What should be done is the slave should send the command packet and the master should read it properly in order to make the communication valid.

You can go through PSoC Creator code examples SPI_Master_interrupt01 for the implementation of above logic.

Hope this helps !

Thanks and regards

Ganesh

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