Once I realized that I hadn't blown my opamps, I resumed work on my load cell project - schematic attached. I am reading voltage values that make some sense in the context (e.g. values get proportionaly larger when more weight is placed on the cell), but the signal coming off the differential preamp is swinging wildy in value. The SAR readings are therefore swinging wildly too, sometimes even more so than their analog counterparts.
I'm too delirious to ask a more detailed question or do other research at this exact point, but since this is for a project on a tight deadline, I thought I'd at least get the conversation started.
Even though you have not completely fried your OpAmps, you still might have damaged the pins. Then this might be the reason that it doesn't work as expected. Can you try with a board thats surely not damaged? Or try the project to use OpAmps / pins that are surely not affected?
Both these ap notes odissey1 mentioned have severe errors in them due to the fact
the PGA G matching is very poor, hence CMR in the IA severly crippled. Don't implement
an IA that way, either 2 or 3 OpAmp versions. An analysis follows.
http://www.cypress.com/?app=forum&id=0&rID=82151 IA Analysis Matlab
Some questions -
1) What is matching accuracy of your 120K Rfdbk resistors ? Even if they have
great matching do the analysis of Aol G matching for the OpAmps, might not
be good enough for your design.
2) What is pk-pk A/D result noise you are getting ?
3) Using a DSO, infinite persistence, look at A/D inputs to see what
total noise looks like into A/D
4) Ground loops present ?
Thank you to everyone for the assistance.
To answer Dana's questions, I have attached a scope shot.
1. Resistors are not matched. Once I recalculate the gain necessary, I will order some resistor networks or precision-matched resistors ASAP.
2. Noise is as high as 60 mV peak-to-peak based on the attached scope shot, a 6% error in a 1.024 V measuring range.
3. Also from the scope shot, noise appears to be largely 100 MHz sinusoid with other random noise.
4. I will check for ground loops. Since the source of the noise seems to be external RF (nothing on the board is running faster than 24 MHz), ground loops might be a likely culprit.
Polymer caps for bulk bypass best, ~ 1 order magnitude better f vs Z
curves, to replace traditional tants. Look at actual datasheets, same
for ceramics, not all caps are as 'good" as we assume.
Some useful ref material on PCB layout and noise....
From tech support -
The front-end of the SAR ADC can be modeled as a first-order RC (low-pass) network- with R = 2.2
kohm and C = 10pF. So, R = 2.2kohm is not really the net input resistance.
And the input impedance of the SAR is a function of the sampling rate and is given by, Zin = 1/ (fs*C),
where C = 10pF.
We should not take the 2.2Kohm as the input resistance of the SAR as it is.
Thank you very much for doing all this analysis. Since I utimately want to minimize off-PSoC components, it will be put to good use.
In the interest of meeting a tight deadline for an in-process demonstration, however, I thought of using an INA826 I have handy to pre-condition the sensor signal, and then going straight in to the PSoC SAR ADC as shown in the attached image. This circuit is not built yet nor are the resistor and cap values calculated yet.
A few questions I have if this is even worth pursuing:
Thank you again for all the help.
No, I think the INA826 takes care of that problem, eg. presenting a low z Vx source to the SAR
I am sure the Vref of INA should be bypassed and at Vdda / 2 to maximize dynamic range.
There is another problem with this part, its input does not common mode to positive rail.
Is that OK with your expected output of the bridge ? The Caps C1 and C2 should be OK
to help noise suppression as long as the latency of a reading due to bridge to C1/C2
settling time OK.
You could synch the SAR be selecting trigger mode and using PSOC comparator from excite
signal to generate the Trigger.
Again - thank you!
I will try a few different schemes over the next few days to see which gives the best practical results, but I think I will initially focus on the alternating excite voltage because that provides some noise cancelation while also increasing dynamic range. I'd also gotten that working once before with the INA826 and a different microcontroller, except that micro would lock up after a while, so I didn't pursue develpment on it further once I moved to the PSoC.
I will report which scheme I end up using once I make that decision.
Use a Star ground for all the analog devices and also you might try a shielded area ground on the inputs. A star ground is one where all the analog device are tied to one point on the board. Also a shielded area ground has The input trace surrounded by a ground shield which is tried to star ground. Also it is hard to get good fidelity with a bread boad or other temporary wiring setups. I assume that you have followed the Cypress layout guide for the PSOC device and have the ground planes and by pass caps. You could also add a Ferrite bead on the power leads.