I've got a large, constant delay in getting a shift out value out of a datapath operation, regardless of the given clock. Why?

[user_443952341]

I'm designing a USB-based driver for WS2812 LEDs. As a part of the project I need to serialize some data but unfortunately the delay between entering a shifting operation in a datapath and getting a bit on the 'Shift Out' output is prohibitively large (26us). It doesn't deviate from this value by more than 1us, regardless of the speed of the clock I feed the datapath with. Also, I don't have any additional logic between the output I read and the datapath's shift out. Is this delay an intrinsic part of the datapath design? It seems really excessive, given the usual order of magnitude of propagation delays in the timing analysis (~30ns), and prevents me from operating the UDB component at periods longer than that 26us.

[Ekta_N]

Hello

How did you measure the delay? If possible can you share your project  ?

[user_443952341 · Accepted solution]

I solved the mystery and it turned out to be a silly problem. I was reading the 'delayed' output off a pin which in the particular kit I am using turns out to be grounded via a capacitor (for use with the SAR). And so my digital output was low-passed with a constant-ish slope which wasn't directly visible on a purely digital logic analyser. Throwing the output onto a different pin solved the issue.

Lessons learned:

• Digital Logic analysers often don't tell the whole story (especially if miscellaneous EE effects are involved)
• Don't assume that just because a kit's pin looks like a GPIO and can be configured as such by the IDE it actually is a GPIO