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As per spec, the master is expected to send a break field of at least 13 nominal bit times of dominant value. Sending 11.3 bit times could be a violation of the LIN spec.
However, even though master will keep the bus voltage at Low for 13 bit times minimum, the slave should get ready by 11bit time, to receive any data. You can change the Break detection threshold (bit times) in the configurator to 12 or more if you feel the slave clock is not accurate.