HFCLK will be changed during each write to a flash row and will impact i2s communication

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Anonymous
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i capture audio data through i2s interface,and store audio data to psoc internal flash。but writing flash will impact i2s communication,how can i avoid this problem?

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HeLi_263931
Level 8
Level 8
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According to the system reference guide, this should happen only on the 4000, 4100 BLE and 4200 BLE devices. Which one are you using?

   

And how to you write to flash? Do you use the  CySysFlashWriteRow system call?

   

(And since the amount of flash memory is limited in the PSoC4 devices - what is your use case? Could it be an option to use external memory, e.g. a Cypress FRAM device?)

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Anonymous
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i use psoc 4200 ble ;

   

yes,i use the api of CySysFlashWriteRow to store audio data;do you know other apis to call?

   

we want low cost product,so will not consider fram device now。

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HeLi_263931
Level 8
Level 8
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For the 4200BLE the doc says the HFCLK will be switched over to 48MHz. So I think that a normal HFCLK of 48MHz might work for you.

   

The comment in the generated code reads:

   
    * The FM-Lite IP uses the IMO at 48MHz for the pump clock and SPC timer     * clock. The PUMP_SEL and HF clock must be set to IMO before calling Flash     * write or erase operation.
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HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

AFAIK there is no other API. Also note that the flash write operation disables all interrupts during write, that might affect your operation. (Though it might be asynchronous, I did not read into the code too deeply)

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