Dynamic change of reference voltage for monitoring two signals (PSOC4)

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Anonymous
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Hello All,

   

I am new to PSOC so please bear with me if this question seems very simple 🙂  I am looking for measuring a signal and battery voltage (for battery monitoring) at the same time.  For battery monitoring the reference voltage is fixed but for the signal I should be able to change the reference voltage at run time.  Is that possible?  Also, for the signal voltage I need to use a comparator so that minimum code is written and all is done by hardware is meausre number of pulses.  I found one example that for that as attached but note sure how -ve of LPComp_1 is driven here by SAR.  Could anybody please help?  

   

Thank a lot,

   

-Gitesh

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ETRO_SSN583
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You could use a TCPWM and a external R-C integrator/LPF to develop a variable ref

   

voltage that can be fed back to the comparator.

   

 

   

Attached considerations in the R-C network design for PWM.

   

 

   

Regards, Dana.

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Bob_Marlowe
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Welcome in the forum, Gitesh!

   

You may generate a reference voltage with the internal IDAC and an external resistor, feeding the comparator (with hysteresis) to generate a clean signal. This can be used to count time between pulses or to count pulses within a given time.

   

The battery level is measured best, as you already said) with the SAR.

   

You posted your question in a forum for PSoC4 BLE - chips which are able to transmit data via integrated Bluetooth Low Energy to a smartphone or to another PSoC BLE chip.

   

 

   

Bob

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Anonymous
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Thank you Bob.  Yes, IDAC approach looks good but can I do it using a single SAR for both?  I would like to save up IDAC for rainy days 🙂  I am using PSOC4 BLE itself.  Maybe I tagged it wrongly to PSOC4.

   

-Gitesh

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ETRO_SSN583
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You could use a TCPWM and a external R-C integrator/LPF to develop a variable ref

   

voltage that can be fed back to the comparator.

   

 

   

Attached considerations in the R-C network design for PWM.

   

 

   

Regards, Dana.

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Anonymous
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Wow! This is one more great way.  Thanks dannaknight.  

   

I came across this  one more hack - http://www.cypress.com/blog/psoc-hacker-blog/measuring-vdd-battery-volts-psoc4?source=search&keyword...

   

One more channel in ADC SAR seq...one for signal and another for battery.  Both will be dynamically changed for input channel and vref.  

   

Regards,

   

-Gitesh

   

 

   

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ETRO_SSN583
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One item of question is placing a cap on ref buffer output, is that a stable

   

configuration for PSOC ref amp ? Quick way of checking, do some

   

code, mux the cap onto the ref buffer out, and look at the step response

   

of the ref buffer to charging the cap. if its largely RC in appearance then

   

phase margin is safe, if lots of ringing (indication poor phase margin) then

   

not so good. A way of overcoming this is a series R into cap, and allow for

   

more delay in charging cap.

   

 

   

To do the test properly an external low Rdson MOSFET switching cap to

   

ground would be preferred way to look at time domain response as internal

   

muxs tend to have a relatively high Rdson.

   

 

   

Another way would be place the cap onto pin, and using a mux connect a

   

load to ground and watch the step response from the load change.

   

 

   

Regards, Dana.

Anonymous
Not applicable

Thanks Dana.  I will check this out.

   

Regards,

   

-Gitesh

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