I am using a shift register to send out a bit stream (about 2000 bits at 3.3MHZ) which has very tight timing requirements.
The code to write to the shift register is executed inside a critical section.
Without CapSense, everything works fine.
With CapSense, timing problems arise. I was supposing that the interrupt of the CapSense leads to these problems, but other means to disable interrupts like CyGlobalIntDisable have no effect either. I am running out of ideas to solve this problem. Any ideas?
A sample project would help us to debug your issue. Is it possible for you to share a sample project focusing on the issue?
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