Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
Hi,this problem is different from the RTC post, I'm just trying to do a simple debouncer circuit to test an issue. PSOC 3.2 creater PSOC 4M/4200M pioneerkit -44 version System clock is HFCLK48Mhz DEvice selected isCY8C4247AZI-M485 which is what the chip is on the M version of the pioneer kit. When I do a regular clock of say 100 hz, I get this message: Unable to create a divider of 480000 for clock "SwClock." The maximum possible divider for this device is 65536. Too large of or too many clock dividers requested. There is a maximum number of clock dividers (used for digital, analog, and fixed function clocks) available depending on the device selected. I can't change the souce from the HFCLock and I can't change anything in the design wide clock screen to have this clock get its source from the 32khz LFCLK. I know from the datasheet that there are 16 dividers so I don't know why it won't let me create a low frq clock. The examples projects don't work for this pioneer kit ONly earlier kits. I even looked at http://www.cypress.com/blog/psoc-sensei-blog clock example. I tried adding another clock to divide the 48mhz down some, but when I add the second clock, it doesn't give me the first clock as a choice for a source. Only Auto and or HFCLock. Even under the existing tab it doesn't list the first clock So how do I use a really low freq clock like I've seen used onother kits?
Hi Bob, I can try that, butyeah that consumes additional resources . The issue it seems is this Initially Aligns too settin which I can't change. Its not even listed in the datasheet !?! See attached IT aligns to the 48MH clock ,even with the Source set to auto. So it can't divide down when I do a project for the regular pioneer kit 4200 and build it, I can do a10 Hz, evena 2hz clock because its chaining the dividers. It won't do it with the 4200M Sems like a bit of bug issue to me if I can't change the source.
Hmma and while this isn't related to the clock bug issue, I just realized the RAspPI header on the -044 kit only has 26 pins. Making it compatible only with the older RaspiPI's. The newer RaspiPi's have 40 pin headers. A design overlook or intentionial? The documentation needs to differentiate between that and not just say compatible with RaspPi.
Thanks guys! Thouh at first I couldn't get either suggestion to work. Then I found the Freq Divider componet and set it to div 8 a clock singal of 800hz. STill didn't work. I created a clock pin to measure the clock after the Freq Div component and into a TFF that had in between the debouncer and LED and it was at 100 hz. So it wasn't that Then I checked my input pin and realized I was still usiing the Strong Drive for Cmos. Changed to pull up resistor confiuration and now it works for all
Yes sir. Though I wasn't using the LFCLK, but the 48mhz HFCLk and had it set to 800 hz. Then I had the freq divider set at 8. In a real application,would there a performance difference between using LFCLK vs HFCLk?