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PSoC 4 MCU

Anonymous
Not applicable

We have a component on the I2C bus which requires about 60us delay from SCL and SDA line pull down until clock and data begin to send.  How is this possible to configure?

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Esteemed Contributor II

Program the ss-line yourself. Before each transaction pull your ss-line low and manage your delay using CyDelay(). When transaction is finished (there is an API to check with) release (set to high) the ss-line again.

   

 

   

Bob

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5 Replies
Esteemed Contributor II

Program the ss-line yourself. Before each transaction pull your ss-line low and manage your delay using CyDelay(). When transaction is finished (there is an API to check with) release (set to high) the ss-line again.

   

 

   

Bob

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Anonymous
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Which API?

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Anonymous
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What command pulls the ss-line high or low?

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Esteemed Contributor II

Because it is your ss-line a simple pin_write(0) will pull the signal low.

   

For the API, search in I2C datasheet for the status. Since there are more than one different I2C implementations I cannot tell which.

   

 

   

Bob

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Anonymous
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Still a bit unclear as to how to toggle ss-line?

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