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We have a component on the I2C bus which requires about 60us delay from SCL and SDA line pull down until clock and data begin to send. How is this possible to configure?
Program the ss-line yourself. Before each transaction pull your ss-line low and manage your delay using CyDelay(). When transaction is finished (there is an API to check with) release (set to high) the ss-line again.
Program the ss-line yourself. Before each transaction pull your ss-line low and manage your delay using CyDelay(). When transaction is finished (there is an API to check with) release (set to high) the ss-line again.
