CY8C4245PVA-452Z: Input of intermediate voltage to High-Z Analog mode

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KaKo_4074056
Level 4
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Distributor - Marubun (Japan)
First like given First solution authored 25 replies posted

Hi,

After reset, GPIO of PSoC4 is initialized to High-Z Analog mode and the digital input buffer is turned off. At this time, I don't think that there is a problem even if an intermediate voltage of 1.8V is input to GPIO at VDD 3.3V operation. Is this correct? Due to the circuit configuration of the board, this state occurs at initialization. Thank you.

Best regards,

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1 Solution

KaKo,

By disabling the digital input buffer, it will prevent the potential of cross-conduction.

Len
"Engineering is an Art. The Art of Compromise."

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6 Replies
Len_CONSULTRON
Level 9
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Beta tester 500 solutions authored 1000 replies posted

KaKo,

Yes.  By default all GPIO are set to Hi-Z analog at reset and the Digital input buffer is disabled.

As you pointed out if the input was somewhere between 0.7*VDD to 0.3V*VDD, a digital input buffer could be in linear mode causing the input to consume more than the expected current (< 0.1uA) .   This would be a problem if this occurred if the PSoC was placed in a low power mode.

Len
"Engineering is an Art. The Art of Compromise."
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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello @KaKo_4074056 

Could you please let us know what are you using the GPIO pin for and is the GPIO pin connected to some peripheral?

In case you are using this pin for digital purpose then as mentioned by Len for the input to be 1 the voltage on the pin should be 0.7*VDD or above and for the input to be zero the voltage should be less than or equal to 0.3V*VDD.

Also please let us know if you are putting the PSoC device to low power mode?

Thanks and Regards

Ekta

 

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

KaKo,

Allow me to "entertain" with a little piece of engineering experience.

As an Automotive EE, I had a experience where the design required < 100uA when in low-power mode.

The design when entering low power mode immediately when below 100uA when things were turned off.  Except I noticed that within about 3 seconds of entering this mode, the current shot up to about 300uA for about 3 seconds then fell to less than 100uA and remained there.

The Root Cause:  There was one GPIO configured to be digital input after reset.   This GPIO pin had a relatively large capacitor (>200uF) on it.   What was happening to cause the unexpected current surge during low-power mode was in this mode we turned off the source voltage to the cap.  (The source voltage was VBAT @ 12V.)   Due to the VDD scaling resistors on this pin, the capacitor was slowly discharging.   When the voltage on the pin reach somewhere below 0.7V*VDD, the digital input buffer was in the linear region.   This caused both the High input FET and Low input FET to partially conduct causing cross-conduction.   R_Hon and R_Lon  were partially ON.

Len_CONSULTRON_0-1620741245887.png

This cross-conduction continued until the input voltage from the discharging cap reached somewhere near 0.3*VDD.  At which time the current again met the < 100uA requirement.

The fix for us was to change the GPIO drive mode assignment to Hi-Z analog just before low-power mode and to return it to Digital Input after wakeup.

Len
"Engineering is an Art. The Art of Compromise."
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KaKo_4074056
Level 4
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Distributor - Marubun (Japan)
First like given First solution authored 25 replies posted

Hi Len, Ekta,

Thank you for the reply. Does it mean that a through-current flows through the input buffer when an intermediate voltage is input to the pin, even if the input buffer is disabled?

Pin12 is used as UART-TX in the application, but it's initialized to default GPIO (P3.1) after reset. The 1.8V generated by the external pullup is input during used as GPIO (High-Z analog). I'll get back to you on the details.

Best regards,

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KaKo,

By disabling the digital input buffer, it will prevent the potential of cross-conduction.

Len
"Engineering is an Art. The Art of Compromise."
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KaKo_4074056
Level 4
Level 4
Distributor - Marubun (Japan)
First like given First solution authored 25 replies posted

Len,

Thank you for your information and experience. That 1.8V from the connected level shifter (1.8V-3.3V) is coming into pin11. The same phenomenon has seen not only pin12 but also pin11 (used for UART-RX in the application). Therefore, it seems that they'll be needed pull-up resistors with the pin anyway. Thank you.

Best regards,

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