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PSoC 4 MCU

New Contributor

hello, I am trying to understand the battery level with voltage divider in PSoC4 BLE. As I have found in one project we use a voltage divider with a cap and an opamp with unity gain (buffer). Why do we need a capacitor (and what value must have?) in the voltage divider? Why the ADC configuration as Vref: Vdda/2, bypassing.  What does it mean Vref bypassing? Can someone explains the whole procedure? Please take into account that the Vdd is a regulator output...

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Moderator
Moderator

Hello Dimitris,

I am not sure which project you are using exactly . I can give comments based on the schematic you have attached. First of all the capacitor after your voltage divider looks like a filtering capacitor. This low pas filter will have a cut-off frequncy, fc = 1/(2*pi*(R1||R2)C) . This may be needed when you are using a switched mode regulator. Essentially you will remove any glitches from the supply from appearing using this filter. You are buffering this VDDA/2 point and is using it as the analog ground in your design. This will give you complete swing for the output(from 0 to VDDA). Your whole analog circuit is using this point as the analog ground if you observe the circuit. One of the end differential terminal is also this point.

Now bypassing is SAR ADC architecture will help you to work in a higher sample rate. Normally the maximum data rate allowable by the ADC is limited according to reference you are using. From the chip analog system point of view the with bypass capacitor the noise introduced is lesser, which will ensure error free working of all the analog components. Without the bypass capacitor the limitation will be the sampling rate. With a bypass cap, the system will be more robust with less error and interference.

Now if your application is just to know battery voltage level with PSoC 4 BLE, there is a battery level measurement example code available in PSoC Creator(File-> Code Example -> BLE_Battery_Level). Here the normal measurement method is not used.

Best Regards,

Vasanth

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8 Replies
Moderator
Moderator

Hello Dimitris,

I am not sure which project you are using exactly . I can give comments based on the schematic you have attached. First of all the capacitor after your voltage divider looks like a filtering capacitor. This low pas filter will have a cut-off frequncy, fc = 1/(2*pi*(R1||R2)C) . This may be needed when you are using a switched mode regulator. Essentially you will remove any glitches from the supply from appearing using this filter. You are buffering this VDDA/2 point and is using it as the analog ground in your design. This will give you complete swing for the output(from 0 to VDDA). Your whole analog circuit is using this point as the analog ground if you observe the circuit. One of the end differential terminal is also this point.

Now bypassing is SAR ADC architecture will help you to work in a higher sample rate. Normally the maximum data rate allowable by the ADC is limited according to reference you are using. From the chip analog system point of view the with bypass capacitor the noise introduced is lesser, which will ensure error free working of all the analog components. Without the bypass capacitor the limitation will be the sampling rate. With a bypass cap, the system will be more robust with less error and interference.

Now if your application is just to know battery voltage level with PSoC 4 BLE, there is a battery level measurement example code available in PSoC Creator(File-> Code Example -> BLE_Battery_Level). Here the normal measurement method is not used.

Best Regards,

Vasanth

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New Contributor

Hello Vasanth,

Very useful you comments...

I would like to add that the project I am using is Optical Heart Rate Monitor. As far as I can understand ADC can have multiple sources of Vref based on SAREF diagram. By using Vdda/2, bypassing in ADC configuration I think that someone can measure VDDA and also have and external Vref with bypassing cap (not showing in top design) for comparison. Is there any way to measure battery level with internal Vref & voltage divider? What kind of ADC config must be used? In the PCB we have no option to have Vref 1024mV as external Vref...Our regulator output is 3.3V.What you suggest?

schematic.png

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New Contributor II

I have just tested battery measurement on cy8ckit-042-ble-a. Since I don't want to waste even a single uA all the time (the device needs to run years on CR2032), I can't use a voltage divider from Vcc to GND. I got good success using a voltage divider from VCC to a pin on PSoC. When I measure I output low to that pin. I get good accuracy with 300 kohm + 100 kohm divider, and the internal 1.024 V reference (bypassed on Vref pin on the PCB. I used single ended and VSS as negative input, 128 samples averaged, hardware trigger and 1736 SPS. You need to select AVG from channels tab. I got 3.37 V while my multimeter shows maybe 3.385 V. Maybe because the measurement was not a steady state and the voltage dropped a few 0.01 V during the measurement (processor is in deep sleep mostly). That was without any adjustments and no cap on voltage divider.

I tested with different samples averaged and SPS. Some gave a bit worse accuracy (e.g. 3.30 V) many were quite equal. The measurement takes less than 1 ms and I plan to do that once per minute or less. So it will have less than 0.1 uA average consumption.

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Moderator
Moderator

Hello Dimitris,

The SAR ADC have multiple Vref options. But measuring VDDA with VDDA/2 reference will not be useful. As VDDA/2 is derived from VDDA with the help of a voltage divider, these voltages are going to proportional. So the counts you are getting out of it will be the same. If you have access to an external voltage reference, any measurement with VDDA or VDDA/2 will give you and idea of the drop in battery voltage. The result count will also increase with the decrease in battery voltage, which is there reference. Now if we could use the internal Vref for this purpose, it would have been much cleaner. But according to SAR ADC architecture the VREF pin in the chip exposes the reference voltage of the ADC in bypassed mode. When the reference is not in bypassed mode this pin is not exposed. So if the ADC is working in VDDA/2 bypassed mode, there is no way to get Vref voltage out of the chip. BLE_Battery_Level example I have mentioned uses a smart of dynamically changing source to solve this problem.

Anyways in your case as you have access to an external reference I think the measurement should be possible. You can also explore the methods suggested by Joakim.

Best Regards,

Vasanth

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New Contributor II

VDD was from a regulator, so it could be used as a reference while measuring the battery voltage. Maybe the one suplying the regulator. Depending on the regulator the internal 1.024 V may be more accurate.

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New Contributor

Hello Vasanth,

thank you for your post

We want 2 channels in ADC inside CYBLE-224110-00 module.One for battery level estimation and the other for our signal.

For our analogue signal we need definitely 8KSPS in one channel. This lead us to have a high Vref for greater dynamic region (Vref=VDDA)

Our battery has maximum output power after charge 4,2V and nominal 3,7V. We have no external Vref. What is optimum way to measure this battery  level...The external Vref is the only solution (and what value must have?)

Thank you in advance

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New Contributor

I forgot to mention that our regulator give us output VDDA=3,3V

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New Contributor II

You can discharge Li-ion below 3.3 V and there will be some drop off at the regulator. So you have no way of know whether you have 3.4 V at the battery and 3.3 V after the regulator vs. 2.8/2.72 V. If you need to discharge and know the battery voltage below 3.3 + drop off, you must use some other reference.

You haven't said how critical current consumption is in your application.

Since there is likely no need to measure battery voltage constantly, you can measure your analogue signal at 8 kSPS all the time using VDD as a reference and then switch to internal 1.024 V reference and measure battery voltage say once per minute or ten minutes etc. That will obviously cause a ~1 ms break in your analogue measurement.

The same consideration about low battery voltage may affect your analogue measurement as well. Regulator voltage will drop with lower battery voltage. Is the analogue voltage ratiometric? If not, you may need to use 1.024 V or external reference low enough not to be affected by lower battery voltage.