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PSoC 4 MCU

Anonymous
Not applicable

Hi all.

   

I managed to create my first PSoC custom component. It is written in verilog, and it contains a status and a control register, along with a datapath. Now, I'm trying to figure out how to write my API files so I can access these 2 registers from the CPU code. I know how to have the IDE create the files (that part is well-documented), but don't know what to put inside my .c and .h files to get to the underlying hardware.

   

In my project's cyfitter.h file, I see a bunch of long and scary #define names for the registers that appear in my instatiated, custom, verilog component. I don't really know where to begin to wrap these in an API. Since I am using the standard status and control registers inside my verilog code, I was *hopeful* that APIs would be auto-generated for those, and then I would just need to manually create a wrapper API at my componet level to call the easy read/write API of the status and control register components. No such luck.

   

Is there any help anyone can offer on how to make an API for a verilog custom coponent that needs to access its embedded status and control register components? This would seem like a pretty common use-case to me, but I'm VERY new to PSoC. 

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JoMe_264151
Expert II

In the Component Author Guide chapter 6.4 Complete the .h File you'll find a table of generated #defines for accessing the UDB registers. To avoid those cryptic long names I #defined them anew with more descriptive names.

   

 

   

Bob

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odissey1
Honored Contributor II

Accessing control Reg is quite easy. Below is API snapshot from custom verilog component, showing access to Control registers

   

 

   

*.C file

   

#include <`$INSTANCE_NAME`.h>


//===========================================================================
void `$INSTANCE_NAME`_SetFrequency( double freq )
{ long phase;
   
    `$INSTANCE_NAME`_ControlStrobe_Write(0);    // ensure strobe to inactive

    //phase= (long)(2.0*freq/Fdiv);                    // calculate phase
    phase= (long)(freq/Fdiv);

    `$INSTANCE_NAME`_ControlPhase1_Write( phase&0xFF );        // write phase
    `$INSTANCE_NAME`_ControlPhase2_Write((phase>> 8)&0xFF );
    `$INSTANCE_NAME`_ControlPhase3_Write((phase>>16)&0xFF );
   
    `$INSTANCE_NAME`_ControlStrobe_Write(1);    // load phase
    `$INSTANCE_NAME`_ControlStrobe_Write(0);    // inactivate storobe
}

 

   

Attached is full project.

   

 

   

Details can be found in training videos:

   


PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Intro to Component API Generation
PSoC Creator 113: PLD Based Verilog Components

   

regards,

   

odissey1

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Anonymous
Not applicable

Thanks for the replies.

   

I'm looking at your custom component, and see something that is quite different from what I was trying to do.

   

You have a verilog component called IQ_Core, which instantiates no control or status registers. You use IQ_Core in schematic macro called IQ_DDS, and in that macro you create your control registers and wire them up to IQ_Core. Then, you have generated code (automatic from Creator!) that gives you access to the high-level control register API. This is in the generated source code files called (for example) DDS1_ControlPhase1.h. At that point, it is easy to build on the generated API to get an overall custom component API for IQ_DDS.

   

In my case, I have no schematic macro encapsulating my Verilog. I just have a Verilog file and a symbol file. Inside my Verilog, I instantiate my control and status register. As such, Cypress does not generate any API files for those registers. All I get is ugly #defines related to the registers inside my generated cyfitter.h.

   

So, obvious follow up question, am I just be silly not creating a schematic macro and putting my control and status register in there instead of in my Verilog??? I asssume I could do that, then just create corresponding input and output in my Verilog module, wire it up, and get some pretty API code automatically for my registers (since they would be instatiated by Creator, and not by my Verilog code).

   

I may try this. But I already foresee another issue around accessing my datapath registers. Since my datapath can only be instantiated inside the Verilog, I'm still going to just have a bunch of ugly #defines for the DP.

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JoMe_264151
Expert II

There are no APIs generated automatically, but you can deliver templates from which the API-files are generated for every instantiation of your module. See chapter 6 of the "Component Author Guide".

   

 

   

Bob

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odissey1
Honored Contributor II

@BrianHo

   

please post your solution once ready. Here only few examples on Verilog available.

   

odissey1

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Anonymous
Not applicable

Brian,

   

I, too, would like to see your result, if you'd be interested in sharing it.  Thanks!

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odissey1
Honored Contributor II

jrsharp,

   

attached example of direct write access from main.C code to a control register, instantiated inside custom Verilog component.

   

odissey1

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