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PSoC 4 MCU

Anonymous
Not applicable

 Hello All,

   

I am tring to create a signal generator that produces a 80kHz square wave that I can adjust +/- 1.5kHz in 1 to 2 Hz steps using a potentiometer that I am sampling. Ideally I could also vary the duty cycle of said waveform also.

   

I tried using a 24MHz clock into a PWM and that gave me the ability to set the period and the compare that gave me control over the freq and duty cycle.  But the steps are 240Hz.

   

Any input/ideas would be greatly appreciated.

   

Sean

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16 Replies
Anonymous
Not applicable
        Hi sean   
Most adapted idea is DDS, Direct Digital Synthesis   
Its need accumulator that adding number of phase.   
Its can generate accurate frequency by 1Hz step.   
Maybe able to build by CPLD in PSoC   
Sorry, I dont know how to in detail.   
Might be someone help us.   
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PrMa_264311
New Contributor II

 Hi Sean,

   

As PSoC73 mentioned, a DDS-like implementation is the best way to go. You don't have to do it in hardware, i have built them in saftware with great success. Depending upon your implementation, you can get sub-Hz resolution. But here's the caveat. The AVERAGE frequency will be almost exactly what you want. The actual frequency from pulse to pulse will vary a bit. This is because you can't do better than the pulse-width of your system clock. There are a few good articles on DDS implementation in EDN. Here is one link.

   

 

   

http://www.edn.com/design/analog/4312999/Microcontroller-provides-an-alternative-to-DDS-item-2

   

 

   

If you use this implementation, just toggle the output pin every time the accumulator overflows.

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PrMa_264311
New Contributor II

The article I was looking for is in Circuit Cellar, but it's behind a paywall.  Here's one more reference, from National Instruments, which should help more than the last one.

   

 

   

http://www.ni.com/white-paper/5516/en/

   

 

   

For an in-depth discussion, see this article from Analog Devices:

   

http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf

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HeLi_263931
Honored Contributor II

You need a numerically controlled oscillator (NCO). There is a PSoC5 implementation available here: http://www.cypress.com/?rID=39408&cache=0, so you can start from there. I'm not sure whether the PSoC4 has enough UDB resources to implement it, though.

   

But if it fits in, it will allow you really fine frequency control.

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ETRO_SSN583
Esteemed Contributor

Before forum can really help you would need to provide target accuracy

   

of generated frequency. And same for step size accuracy. I am assuming

   

monotonic behavior, eg linearity has to be better than 1/2 step size in period.

   

 

   

A PWM solution would have to be 17 bits minimum, so you wind up needing 24

   

bit PWM as they come in byte increments. Verilog solution only way in PSOC 4.

   

Then depending on accuracy you need a 2^^24 Hz clock into it, accurate to your

   

spec.

   

 

   

As pointed out DDS approach certainly doable, but external. An internal DDS

   

approach with a 1 hz step implies a table size > 160,000 elements, and that

   

does not have Duty Cycle control.

   

 

   

Note external solution there are DDS parts in the $ 1 - $ 2 range at that frequency

   

in volume.

   

 

   

Then there is this approach http://www.cypress.com/?app=forum&id=4749&rID=83373

   

 

   

And again, accuracy spec controls design choices.

   

 

   

Regards, Dana.

   

 

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Anonymous
Not applicable

 Guys, Sean nees only a square wave so no need for big tables

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ETRO_SSN583
Esteemed Contributor

This I believe is what he asked for -

   

 

   

"I am tring to create a signal generator that produces a 80kHz square wave that I can adjust +/- 1.5kHz in 1 to 2 Hz steps using a potentiometer that I am sampling. Ideally I could also vary the duty cycle of said waveform also."

   

 

   

Regards, Dana.

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PrMa_264311
New Contributor II

 The solution I proposed requires no LUT. It requires two accumulators (though one will do), and an interrupt. It can be done in hardware verilog (I built it in VHDL), or remain entirely in software. I've used the same technique to do demodulation of a signal. 

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ETRO_SSN583
Esteemed Contributor

@Manjagu, my apologies, I skiped over your post thinking just another DDS

   

approach. That approach is quite interesting, even canonical it seems. And

   

in light of the fact the PSOC 4 has a single cycle 32 bit MAC, I am dying to know

   

what max freq can be done by the algorithim.

   

 

   

Regards, Dana.

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rotec_264361
New Contributor II

@ Dana

   

PSoC 4 has a single cycle 32-bit MAC? I did not know that but then again, I am not a PSoC 4 specialist.

   

This is what I do know: Cortex-M4 has a single cycle MAC and currently Cortex-M4 is the most powerful implementation of Cortex-M.

   

PSoC 4 uses the Cortex-M0 which is almost the smallest and least performant implementation of Cortex-M

   

Is there a hardware implementation of a single cycle 32-bit MAC, multiply and accumulate?

   

If you don't mind to give me a hint where this is documented, I am very interested in DSP algorithms and this is exactly what I've been missing in the current line-up of PSoC devices.

   

Thanks!

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HeLi_263931
Honored Contributor II

The PSoC4 has single-cycle multiply, but not multiply-add. At least that's what is stated in the 4200 series data sheet.

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Anonymous
Not applicable
        As zeta mentioned frequency resolutions depend on bit with of accumulator.   
We need 24bit or 32bit LUT?   
Noway, we just need to have small table, like 8bit   
And assign it from MSB.   
Only voltage accuracy depend upon the table.   
   
However, to access from UDB to the table   
That is difficult, The Warp-Verilog can't do this.   
It is problem of mine.   
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ETRO_SSN583
Esteemed Contributor

@ me2 & hli, thanks hli, I have a bad habit of calling a X a MAC,

   

me2 it is just a multiplier as hli points out in the PSOC 4 family.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

So far, I'm doing on PSoC4 but,     

   

It seems the assignment of UDB is much different with PSoC3 or 5LP     

   

PSoC4 need much number of UBD macro-cell.     

   

So it is impossible but on 5LP working well.     

   

     

            

   

============================================================     

   

PsoC4 resource report      

   

Resource Type                 : Used : Free :  Max :  % Used     

   

============================================================     

   

Digital clock dividers        :    1 :    3 :    4 :  25.00%     

   

Pins                          :    9 :   27 :   36 :  25.00%     

   

UDB Macrocells                :   75 :  -43 :   32 : 234.38% ß-- Too much     

   

Error: mpr.M0014: Resource limit: Maximum number of UDB Macrocells exceeded (max=32, needed=75). (App=cydsfit)     

   

UDB Unique Pterms             :  105 :  -41 :   64 : 164.06%     

   

Error: mpr.M0014: Resource limit: Maximum number of UDB Unique Pterms exceeded (max=64, needed=105). (App=cydsfit)     

   

UDB Total Pterms              :  105 :      :      :     

   

UDB Datapath Cells            :    0 :    4 :    4 :   0.00%     

   

UDB Status Cells              :    1 :    3 :    4 :  25.00%     

   

             Status Registers :    1     

   

UDB Control Cells             :    5 :   -1 :    4 : 125.00%     

   

Error: mpr.M0014: Resource limit: Maximum number of UDB Control Cells exceeded (max=4, needed=5). (App=cydsfit)

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Anonymous
Not applicable

Aha!     

   

I have to correct the previous.     

   

The method of assignment UDB is NOT different.     

   

Just simply, PSoC4 has not enough UDBs.     

   

     

            

   

============================================================     

   

PsoC5LP resource report      

   

Resource Type                 : Used : Free :  Max :  % Used     

   

============================================================     

   

UDB Macrocells                :   73 :  119 :  192 :  38.02% ç same number needs     

   

UDB Unique Pterms             :  105 :  279 :  384 :  27.34%     

   

============================================================     

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Anonymous
Not applicable

Hey, I had uploading DDS module in here  

   

http://www.cypress.com/?app=forum&id=2492&rID=86654

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