24-Channel LED driver

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Anonymous
Not applicable

I'm developing an SPI HAL on the CY8C4247AZI-M485 to communicate with an LED2472G (24-Channel LED driver IC).

The problem: The LED2472G supports a "quasi" SPI protocol.  In addition to the MISO, MOSI and SCLK lines I have to a manage an LE line.  This LE (latch enable) line needs to toggle high for a precise amount of clock cycles during a data transfer.

I've tried approaching this two ways:

1) "Bit bang" the SPI protocol using a timer to have finer control of the LE relative to the clock cycles.  This works but it's not desirable, I'd rather manage this using internal hardware.

2) A PWM that manages both the LE line and an SPI component (driven with DMA):  The PWM's compare interrupt triggers the initial SPI write.  Later the PWM's terminal count interrupt toggles the LE line.  Unfortunately the LE doesn't always toggle high at the correct time relative to the SCLK.

Is there an approach I haven't considered?  Could I somehow modify a hardware component to support an LE line?

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1 Solution
JobinT_31
Employee
Employee
50 solutions authored 25 solutions authored 10 solutions authored

Hi,

Just a suggestion:

Can we try connecting the SCLK line of SPI to the PWM. Then the LE can be generated by PWM component output.

Setting the Period as 24 and compare as 2 [for data latch]

And by simply changing the compare you can select different LE signal 'digital keys'     [Table 7. Digital keys summary    - http://www.st.com/content/ccc/resource/technical/document/datasheet/38/87/8b/7a/c1/cf/4d/36/DM000842...  ]

pastedImage_2.png

Thanks

Jobin GT

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2 Replies
JobinT_31
Employee
Employee
50 solutions authored 25 solutions authored 10 solutions authored

Hi,

Just a suggestion:

Can we try connecting the SCLK line of SPI to the PWM. Then the LE can be generated by PWM component output.

Setting the Period as 24 and compare as 2 [for data latch]

And by simply changing the compare you can select different LE signal 'digital keys'     [Table 7. Digital keys summary    - http://www.st.com/content/ccc/resource/technical/document/datasheet/38/87/8b/7a/c1/cf/4d/36/DM000842...  ]

pastedImage_2.png

Thanks

Jobin GT

Anonymous
Not applicable

Hi,

One or two weeks ago I found a solution that works, somewhat similar to yours.  Instead of a PWM I used a counter component, so the SCLK line is connected to the COUNT of the counter (the SPIM and Counter share the same clock input).  I added a logical 'not' on the COUNT input so the counter would update the LE line before the next rising edge of the SCLK.

I adjust the counter compare value as needed for different LE digital keys.

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