s25fs512 write protect

Anonymous · ‎Sep 17, 2018

Hi,

Currently evaluating this FLASH and attempting to lock registers using the WP# pin, however it's not working as advertised.

Using the WRR command I am able to set SRNV-1[SRWD]=1, which now should follow WP#. I power cycle and can verify

that it is set via UBOOT console using RDSR-1.

What I expect to happen is that if I ground WP# I should NOT be able to change SRNV1, however I am able to toggle this

register even with the pin grounded. What am I missing? Thanks in advance.

Anonymous · ‎Sep 19, 2018

Ok,

Believe we have found the issue, but still don't understand this fully. Our LINUX target boots up in single mode (MISO/MOSI), but when the kernel gets a hold of it, it runs in QUAD mode.

Somewhere along the way, it must have written to CRNV1 and set the QUAD_NV bit for QPI mode. This apparently has no effect on single mode operation, however it seems to prevent IO2 and IO3 to operate as WP# and RESET respectively. Once this was cleared, the write protection worked as expected.

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s25fs512 write protect

s25fs512 write protect

Re: s25fs512 write protect